ltmodem-0.0.5/ 40777 0 0 0 6755710633 11157 5ustar rootrootltmodem-0.0.5/ChangeLog100644 1750 144 1470 6755710344 12443 0ustar users1999-08-16 root * 0.0.5 Added code from Pavel Machek and some tidy ups. Filled in some more gaps. Now incorporates some interrupt handling and DSP access stuff. 1999-07-20 root * 0.0.4 Added suggestions from Pavel Machek and the ability to specify an offset when writing to the ports. 1999-07-05 root * 0.0.3 Added monitoring functions to enable user to select I/O or register monitoring and to set the monitoring interval in milliseconds. Sat Jun 19 01:20:32 EDT 1999 Richard Close * 0.0.2 First "proper" ALPHA release, with ammended README and Changelog files. Added I/O WRITE/READ funcions to 0.0.1 functionality and improved the interface a tiny bit. ltmodem-0.0.5/Makefile100644 1750 144 3531 6755677415 12344 0ustar users# $Id: Makefile,v 1.16 1999/05/19 12:01:26 mj Exp $ # Makefile for Linux PCI Utilities # (c) 1998--1999 Martin Mares #OPT=-O2 -fomit-frame-pointer OPT=-O2 -g CFLAGS=$(OPT) -Wall -W -Wno-parentheses -Wstrict-prototypes -Werror -fcommon ROOT=/ PREFIX=/usr VERSION=0.0.5 SUFFIX= #SUFFIX=-alpha DATE=99-08-15 export all: lib ltmodem lib: lib/config.h $(MAKE) -C lib all lib/config.h: cd lib && ./configure $(PREFIX) $(VERSION) ltmodem: ltmodem.o portIO.o HAL.o common.o irq.o lib/libpci.a ltmodem.o: ltmodem.c ltmodem.h portIO.h HAL.h pciutils.h lib/libpci.a portIO.o: portIO.c portIO.h HAL.h HAL.o: HAL.c HAL.h common.o: common.c pciutils.h lib/libpci.a %.8: %.man sed <$< >$@ "s/@TODAY@/`date -d $(DATE) '+%d %B %Y'`/;s/@VERSION@/ltmodem-$(VERSION)$(SUFFIX)/" clean: rm -f `find . -name "*~" -or -name "*.[oa]" -or -name "\#*\#" -or -name TAGS -or -name core` rm -f ltmodem lib/config.* *.8 rm -rf dist install: all install -m 755 -s ltmodem $(ROOT)/sbin install -m 644 pci.ids $(PREFIX)/share # Remove relics from old versions rm -f $(ROOT)/etc/pci.ids release: sed "s/^\\(Version:[ ]*\\)[0-9.]*/\\1$(VERSION)/;s/^\\(Entered-date:[ ]*\\)[0-9]*/\\1`date -d$(DATE) '+%y%m%d'`/;s/\\(ltmodem-\\)[0-9.]*/\\1$(VERSION)\\./" ltmodem.lsm.new sed "s/^\\(Version:[ ]*\\)[0-9.]*/\\1$(VERSION)/" ltmodem.spec.new sed "s/\\(, version \\).*\./\\1$(VERSION)$(SUFFIX)./" README.new mv ltmodem.lsm.new ltmodem.lsm mv ltmodem.spec.new ltmodem.spec mv README.new README REL=ltmodem-$(VERSION) dist: clean mkdir dist cp -a . dist/$(REL) rm -rf `find dist/$(REL) -name CVS -o -name tmp` dist/$(REL)/dist [ -f dist/$(REL)/lib/header.h ] || cp /usr/src/linux/include/linux/pci.h dist/$(REL)/lib/header.h cd dist ; tar czvvf /tmp/$(REL).tar.gz $(REL) .PHONY: all lib clean install dist man release ltmodem-0.0.5/README100644 1750 144 4011 6755676334 11555 0ustar usersThis package contains the Lucent PCI Modem Utilities, version 0.0.5 By Richard J.M. Close and Pavel Machek These were originally based on the PCI Utilities, version 2.0. Copyright (c) 1997--1999 Martin Mares Please don't hassel Martin with any problems in this code! All files in this package can be freely distributed and used according to the terms of the GNU General Public License, either version 2 or (at your opinion) any newer version. This is the same distribution policy as for the Linux kernel itself -- see /usr/src/linux/COPYING for details. LTModem is a tool used to access PCI based Lucent chipset winmodem. The modem can be interogated, monitored and written to. The current version works only on Linux, but it can be easily extended to work on other systems as well. At some point in the future I will be adding some Lucent specific DSP related functionality, like code transfer to/from the DSP, *IF* I can either reverse engineer the Lucent driver :( or if those lovely, kind, generous people at Lucent release some info. on the subject. The interface is text based and fairly obvious. If in doubt, try it out. FUNCTIONALITY: Detects Lucent PCI modems. Monitor the I/O ports or registers at a specified interval. Write a word to the control register. Write to, then readback from an I/O port (with offset). Note: To quit the continous monitoring function you have to use control-c. INSTALLATION: To compile the package, just run "make_i2sig" then "make". To install it, "make install". To get the benefit of the updated pci.ids file (it has all the Lucent modems I know about) copy the pci.ids file to /usr/share. Alternatlively you could just copy the Lucent device entries across to your existing file. If you have any bug reports or suggestions, send them to the author (NOT Martin!). You might want to look at my web page containing release notes and other news at: http://www.close.u-net.com/. Regards Richard. ltmodem-0.0.5/TODO100644 1750 144 554 6755676563 11361 0ustar users- Find a more elegant way, other than control-c, to quit monitoring. - Improve the user interface, keep it text based though. - Correctly set up initial values for most of the important variables. - Add stuff to allow transfer of code to the board's RAM. - Allow execution of code by DSP. - Find out why inl(port) reads different values to doing inb(port) 4 times!ltmodem-0.0.5/common.c100644 1750 144 3074 6652164547 12333 0ustar users/* * $Id: common.c,v 1.1 1999/01/22 21:04:50 mj Exp $ * * Linux PCI Utilities -- Common Functions * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include #include #include #include "pciutils.h" void __attribute__((noreturn)) die(char *msg, ...) { va_list args; va_start(args, msg); fputs("lspci: ", stderr); vfprintf(stderr, msg, args); fputc('\n', stderr); exit(1); } void * xmalloc(unsigned int howmuch) { void *p = malloc(howmuch); if (!p) die("Unable to allocate %d bytes of memory", howmuch); return p; } int parse_generic_option(int i, struct pci_access *pacc, char *optarg) { switch (i) { #ifdef HAVE_PM_LINUX_PROC case 'P': pacc->method_params[PCI_ACCESS_PROC_BUS_PCI] = optarg; pacc->method = PCI_ACCESS_PROC_BUS_PCI; break; #endif #ifdef HAVE_PM_INTEL_CONF case 'H': if (!strcmp(optarg, "1")) pacc->method = PCI_ACCESS_I386_TYPE1; else if (!strcmp(optarg, "2")) pacc->method = PCI_ACCESS_I386_TYPE2; else die("Unknown hardware configuration type %s", optarg); break; #endif #ifdef HAVE_PM_SYSCALLS case 'S': pacc->method = PCI_ACCESS_SYSCALLS; break; #endif #ifdef HAVE_PM_DUMP case 'F': pacc->method_params[PCI_ACCESS_DUMP] = optarg; pacc->method = PCI_ACCESS_DUMP; break; #endif case 'G': pacc->debugging++; break; default: return 0; } return 1; } ltmodem-0.0.5/i2sig.c100644 0 0 3641 6753710612 12430 0ustar rootroot/* * Copyright 1999 Pavel Machek, distribute under GPL version 2 or later. * * This converts interrupt into signal */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define ID printk( "n2cd: " ) #define MAXDEVS 64 MODULE_AUTHOR("Pavel Machek "); static int pid = 0; MODULE_PARM(pid, "i"); static int irq = 3; MODULE_PARM(irq, "i"); static void enable_now_do(unsigned long unused) { printk( "enough time, enabling interrupt..." ); enable_irq(irq); printk( "enabled\n" ); } static struct timer_list enable_now_timer = {NULL, NULL, 0, 0, enable_now_do}; static void interrupt( int irq, void *dev_id, struct pt_regs *regs ) { printk( "Interrupt %d came...", irq ); kill_proc(pid, SIGUSR1, 1); disable_irq(irq); enable_now_timer.expires = jiffies + HZ; enable_now_timer.prev = enable_now_timer.next = NULL; add_timer(&enable_now_timer); printk( "ok\n" ); } #ifdef MODULE int init_module(void) { printk( "i2sig: V0.1.0, copyright 1999 Pavel Machek\n" ); if (request_irq( irq, interrupt, SA_SHIRQ, "i2sig", (void *) &irq)) { printk( "Can not get IRQ\n" ); return -EAGAIN; } printk( "Success." ); return 0; } void cleanup_module(void) { free_irq(irq, (void *) &irq); } #endif ltmodem-0.0.5/lib/ 40755 1750 144 0 6755710620 11335 5ustar usersltmodem-0.0.5/lib/names.c100644 1750 144 14363 6652164623 12732 0ustar users/* * $Id: names.c,v 1.1 1999/01/22 21:05:33 mj Exp $ * * The PCI Library -- ID to Name Translation * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include #include #include #include #include #include "internal.h" struct nl_entry { struct nl_entry *next; word id1, id2; int cat; byte *name; }; #define NL_VENDOR 0 #define NL_DEVICE 1 #define NL_CLASS 2 #define NL_SUBCLASS 3 #define NL_SUBSYSTEM_VENDOR 4 #define NL_SUBSYSTEM_DEVICE 5 #define HASH_SIZE 1024 static inline unsigned int nl_calc_hash(int cat, int id1, int id2) { unsigned int h; h = id1 ^ id2 ^ (cat << 5); h += (h >> 6); return h & (HASH_SIZE-1); } static struct nl_entry *nl_lookup(struct pci_access *a, int num, int cat, int id1, int id2) { unsigned int h; struct nl_entry *n; if (num) return NULL; h = nl_calc_hash(cat, id1, id2); n = a->nl_hash[h]; while (n && (n->id1 != id1 || n->id2 != id2 || n->cat != cat)) n = n->next; return n; } static int nl_add(struct pci_access *a, int cat, int id1, int id2, byte *text) { unsigned int h = nl_calc_hash(cat, id1, id2); struct nl_entry *n = a->nl_hash[h]; while (n && (n->id1 != id1 || n->id2 != id2 || n->cat != cat)) n = n->next; if (n) return 1; n = pci_malloc(a, sizeof(struct nl_entry)); n->id1 = id1; n->id2 = id2; n->cat = cat; n->name = text; n->next = a->nl_hash[h]; a->nl_hash[h] = n; return 0; } static void err_name_list(struct pci_access *a, char *msg) { a->error("%s: %s: %s\n", a->id_file_name, msg, strerror(errno)); } static void parse_name_list(struct pci_access *a) { byte *p = a->nl_list; byte *q, *r; int lino = 0; unsigned int id1=0, id2=0; int cat, last_cat = -1; while (*p) { lino++; q = p; while (*p && *p != '\n') { if (*p == '#') { *p++ = 0; while (*p && *p != '\n') p++; break; } if (*p == '\t') *p = ' '; p++; } if (*p == '\n') *p++ = 0; if (!*q) continue; r = p; while (r > q && r[-1] == ' ') *--r = 0; r = q; while (*q == ' ') q++; if (r == q) { if (q[0] == 'C' && q[1] == ' ') { if (strlen(q+2) < 3 || q[4] != ' ' || sscanf(q+2, "%x", &id1) != 1) goto parserr; cat = last_cat = NL_CLASS; } else if (q[0] == 'S' && q[1] == ' ') { if (strlen(q+2) < 5 || q[6] != ' ' || sscanf(q+2, "%x", &id1) != 1) goto parserr; cat = last_cat = NL_SUBSYSTEM_VENDOR; q += 2; } else { if (strlen(q) < 5 || q[4] != ' ' || sscanf(q, "%x", &id1) != 1) goto parserr; cat = last_cat = NL_VENDOR; } id2 = 0; } else { if (sscanf(q, "%x", &id2) != 1) goto parserr; if (last_cat < 0) goto parserr; if (last_cat == NL_CLASS) cat = NL_SUBCLASS; else cat = last_cat+1; } q += 4; while (*q == ' ') q++; if (!*q) goto parserr; if (nl_add(a, cat, id1, id2, q)) a->error("%s, line %d: duplicate entry", a->id_file_name, lino); } return; parserr: a->error("%s, line %d: parse error", a->id_file_name, lino); } static void load_name_list(struct pci_access *a) { int fd; struct stat st; fd = open(a->id_file_name, O_RDONLY); if (fd < 0) { a->numeric_ids = 1; return; } if (fstat(fd, &st) < 0) err_name_list(a, "stat"); a->nl_list = pci_malloc(a, st.st_size + 1); if (read(fd, a->nl_list, st.st_size) != st.st_size) err_name_list(a, "read"); a->nl_list[st.st_size] = 0; a->nl_hash = pci_malloc(a, sizeof(struct nl_entry *) * HASH_SIZE); bzero(a->nl_hash, sizeof(struct nl_entry *) * HASH_SIZE); parse_name_list(a); close(fd); } void pci_free_name_list(struct pci_access *a) { pci_mfree(a->nl_list); a->nl_list = NULL; pci_mfree(a->nl_hash); a->nl_hash = NULL; } static int compound_name(struct pci_access *a, int num, char *buf, int size, int cat, int v, int i) { if (!num) { struct nl_entry *e, *e2; e = nl_lookup(a, 0, cat, v, 0); e2 = nl_lookup(a, 0, cat+1, v, i); if (!e) return snprintf(buf, size, "Unknown device %04x:%04x", v, i); else if (!e2) return snprintf(buf, size, "%s: Unknown device %04x", e->name, i); else return snprintf(buf, size, "%s %s", e->name, e2->name); } else return snprintf(buf, size, "%04x:%04x", v, i); } char * pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, u32 arg1, u32 arg2) { int num = a->numeric_ids; int res; struct nl_entry *n; if (flags & PCI_LOOKUP_NUMERIC) { flags &= PCI_LOOKUP_NUMERIC; num = 1; } if (!a->nl_hash && !num) { load_name_list(a); num = a->numeric_ids; } switch (flags) { case PCI_LOOKUP_VENDOR: if (n = nl_lookup(a, num, NL_VENDOR, arg1, 0)) return n->name; else res = snprintf(buf, size, "%04x", arg1); break; case PCI_LOOKUP_DEVICE: if (n = nl_lookup(a, num, NL_DEVICE, arg1, arg2)) return n->name; else res = snprintf(buf, size, "%04x", arg1); break; case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE: res = compound_name(a, num, buf, size, NL_VENDOR, arg1, arg2); break; case PCI_LOOKUP_VENDOR | PCI_LOOKUP_SUBSYSTEM: if (n = nl_lookup(a, num, NL_SUBSYSTEM_VENDOR, arg1, 0)) return n->name; else res = snprintf(buf, size, "%04x", arg1); break; case PCI_LOOKUP_DEVICE | PCI_LOOKUP_SUBSYSTEM: if (n = nl_lookup(a, num, NL_SUBSYSTEM_DEVICE, arg1, arg2)) return n->name; else res = snprintf(buf, size, "%04x", arg1); break; case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE | PCI_LOOKUP_SUBSYSTEM: res = compound_name(a, num, buf, size, NL_SUBSYSTEM_VENDOR, arg1, arg2); break; case PCI_LOOKUP_CLASS: if (n = nl_lookup(a, num, NL_SUBCLASS, arg1 >> 8, arg1 & 0xff)) return n->name; else if (n = nl_lookup(a, num, NL_CLASS, arg1, 0)) res = snprintf(buf, size, "%s [%04x]", n->name, arg1); else res = snprintf(buf, size, "Class %04x", arg1); break; default: return ""; } return (res == size) ? "" : buf; } ltmodem-0.0.5/lib/internal.h100644 1750 144 4040 6652164617 13422 0ustar users/* * $Id: internal.h,v 1.1 1999/01/22 21:05:29 mj Exp $ * * The PCI Library -- Internal Include File * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "pci.h" #ifdef HAVE_PM_LINUX_BYTEORDER_H #include #define cpu_to_le16 __cpu_to_le16 #define cpu_to_le32 __cpu_to_le32 #define le16_to_cpu __le16_to_cpu #define le32_to_cpu __le32_to_cpu #else #include #if __BYTE_ORDER == __BIG_ENDIAN #define cpu_to_le16 swab16 #define cpu_to_le32 swab32 #define le16_to_cpu swab16 #define le32_to_cpu swab32 static inline word swab16(word w) { return (w << 8) | ((w >> 8) & 0xff); } static inline u32 swab32(u32 w) { return ((w & 0xff000000) >> 24) | ((w & 0x00ff0000) >> 8) | ((w & 0x0000ff00) << 8) | ((w & 0x000000ff) << 24); } #else #define cpu_to_le16(x) (x) #define cpu_to_le32(x) (x) #define le16_to_cpu(x) (x) #define le32_to_cpu(x) (x) #endif #endif struct pci_methods { char *name; void (*config)(struct pci_access *); int (*detect)(struct pci_access *); void (*init)(struct pci_access *); void (*cleanup)(struct pci_access *); void (*scan)(struct pci_access *); void (*fill_info)(struct pci_dev *, int flags); int (*read)(struct pci_dev *, int pos, byte *buf, int len); int (*write)(struct pci_dev *, int pos, byte *buf, int len); void (*init_dev)(struct pci_dev *); void (*cleanup_dev)(struct pci_dev *); }; void pci_generic_scan(struct pci_access *); void pci_generic_fill_info(struct pci_dev *, int flags); int pci_generic_block_read(struct pci_dev *, int pos, byte *buf, int len); int pci_generic_block_write(struct pci_dev *, int pos, byte *buf, int len); void *pci_malloc(struct pci_access *, int); void pci_mfree(void *); struct pci_dev *pci_alloc_dev(struct pci_access *); int pci_link_dev(struct pci_access *, struct pci_dev *); extern struct pci_methods pm_intel_conf1, pm_intel_conf2, pm_linux_proc, pm_syscalls, pm_dump; #define UNUSED __attribute__((unused)) ltmodem-0.0.5/lib/pci.h100644 1750 144 11311 6666333361 12377 0ustar users/* * $Id: pci.h,v 1.3 1999/02/28 20:23:11 mj Exp $ * * The PCI Library * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #ifndef _PCI_LIB_H #define _PCI_LIB_H #include "config.h" #ifdef HAVE_OWN_HEADER_H #include "header.h" #else #include #endif /* * Types */ #include typedef __u8 byte; typedef __u8 u8; typedef __u16 word; typedef __u16 u16; typedef __u32 u32; #ifdef HAVE_64BIT_ADDRESS typedef unsigned long long pciaddr_t; #else typedef unsigned long pciaddr_t; #endif /* * PCI Access Structure */ struct pci_methods; struct nl_entry; #define PCI_ACCESS_AUTO 0 /* Autodetection (params: none) */ #define PCI_ACCESS_PROC_BUS_PCI 1 /* Linux /proc/bus/pci (params: path) */ #define PCI_ACCESS_SYSCALLS 2 /* pciconfig_read() syscalls (params: none) */ #define PCI_ACCESS_I386_TYPE1 3 /* i386 ports, type 1 (params: none) */ #define PCI_ACCESS_I386_TYPE2 4 /* i386 ports, type 2 (params: none) */ #define PCI_ACCESS_DUMP 5 /* Dump file (params: filename) */ #define PCI_ACCESS_MAX 6 struct pci_access { /* Options you can change: */ unsigned int method; /* Access method */ char *method_params[PCI_ACCESS_MAX]; /* Parameters for the methods */ int writeable; /* Open in read/write mode */ int buscentric; /* Bus-centric view of the world */ char *id_file_name; /* Name of ID list file */ int numeric_ids; /* Don't resolve device IDs to names */ int debugging; /* Turn on debugging messages */ /* Functions you can override: */ void (*error)(char *msg, ...); /* Write error message and quit */ void (*warning)(char *msg, ...); /* Write a warning message */ void (*debug)(char *msg, ...); /* Write a debugging message */ struct pci_dev *devices; /* Devices found on this bus */ /* Fields used internally: */ struct pci_methods *methods; char *nl_list; /* Name list cache */ struct nl_entry **nl_hash; int fd; /* proc: fd */ int fd_rw; /* proc: fd opened read-write */ struct pci_dev *cached_dev; /* proc: device the fd is for */ }; /* Initialize PCI access */ struct pci_access *pci_alloc(void); void pci_init(struct pci_access *); void pci_cleanup(struct pci_access *); /* Scanning of devices */ void pci_scan_bus(struct pci_access *acc); struct pci_dev *pci_get_dev(struct pci_access *acc, int bus, int dev, int func); /* Raw access to specified device */ void pci_free_dev(struct pci_dev *); /* * Devices */ struct pci_dev { struct pci_dev *next; /* Next device in the chain */ word bus; /* Higher byte can select host bridges */ byte dev, func; /* Device and function */ /* These fields are set by pci_fill_info() */ word vendor_id, device_id; /* Identity of the device */ int irq; /* IRQ number */ pciaddr_t base_addr[6]; /* Base addresses */ pciaddr_t rom_base_addr; /* Expansion ROM base address */ /* Fields used internally: */ struct pci_access *access; struct pci_methods *methods; byte *cache; /* Cached information */ int cache_len; int known_fields; /* Set of info fields that is already known */ int hdrtype; /* Direct methods: header type */ void *aux; /* Auxillary data */ }; #define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3) #define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf) byte pci_read_byte(struct pci_dev *, int pos); /* Access to configuration space */ word pci_read_word(struct pci_dev *, int pos); u32 pci_read_long(struct pci_dev *, int pos); int pci_read_block(struct pci_dev *, int pos, byte *buf, int len); int pci_write_byte(struct pci_dev *, int pos, byte data); int pci_write_word(struct pci_dev *, int pos, word data); int pci_write_long(struct pci_dev *, int pos, u32 data); int pci_write_block(struct pci_dev *, int pos, byte *buf, int len); void pci_fill_info(struct pci_dev *, int flags); /* Fill in device information */ #define PCI_FILL_IDENT 1 #define PCI_FILL_IRQ 2 #define PCI_FILL_BASES 4 #define PCI_FILL_ROM_BASE 8 #define PCI_FILL_RESCAN 0x10000 void pci_setup_cache(struct pci_dev *, byte *cache, int len); /* * Filters */ struct pci_filter { int bus, slot, func; /* -1 = ANY */ int vendor, device; }; void pci_filter_init(struct pci_access *, struct pci_filter *); char *pci_filter_parse_slot(struct pci_filter *, char *); char *pci_filter_parse_id(struct pci_filter *, char *); int pci_filter_match(struct pci_filter *, struct pci_dev *); /* * Device names */ char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, u32 arg1, u32 arg2); void pci_free_name_list(struct pci_access *a); #define PCI_LOOKUP_VENDOR 1 #define PCI_LOOKUP_DEVICE 2 #define PCI_LOOKUP_CLASS 4 #define PCI_LOOKUP_SUBSYSTEM 8 #define PCI_LOOKUP_NUMERIC 0x10000 #endif ltmodem-0.0.5/lib/Makefile100644 1750 144 1373 6652711725 13101 0ustar users# $Id: Makefile,v 1.2 1999/01/24 21:35:35 mj Exp $ # Makefile for The PCI Library # (c) 1999 Martin Mares include config.mk OBJS=access.o generic.o dump.o names.o filter.o INCL=internal.h pci.h config.h ifdef HAVE_PM_LINUX_PROC OBJS += proc.o endif ifdef HAVE_PM_INTEL_CONF OBJS += i386-ports.o endif ifdef HAVE_PM_DUMP OBJS += dump.o endif ifdef HAVE_PM_SYSCALLS OBJS += syscalls.o endif ifdef HAVE_OWN_HEADER_H INCL += header.h endif all: libpci.a libpci.a: $(OBJS) rm -f $@ ar rcs $@ $^ ranlib $@ access.o: access.c $(INCL) i386-ports.o: i386-ports.c $(INCL) proc.o: proc.c $(INCL) generic.o: generic.c $(INCL) syscalls.o: syscalls.c $(INCL) dump.o: dump.c $(INCL) names.o: names.c $(INCL) filter.o: filter.c $(INCL) ltmodem-0.0.5/lib/access.c100644 1750 144 13216 6653625176 13072 0ustar users/* * $Id: access.c,v 1.3 1999/01/27 14:53:02 mj Exp $ * * The PCI Library -- User Access * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include #include #include "internal.h" static struct pci_methods *pci_methods[PCI_ACCESS_MAX] = { NULL, #ifdef HAVE_PM_LINUX_PROC &pm_linux_proc, #else NULL, #endif #ifdef HAVE_PM_SYSCALLS &pm_syscalls, #else NULL, #endif #ifdef HAVE_PM_INTEL_CONF &pm_intel_conf1, &pm_intel_conf2, #else NULL, NULL, #endif #ifdef HAVE_PM_DUMP &pm_dump, #else NULL, #endif }; struct pci_access * pci_alloc(void) { struct pci_access *a = malloc(sizeof(struct pci_access)); int i; bzero(a, sizeof(*a)); a->id_file_name = PATH_PCI_IDS; for(i=0; iconfig) pci_methods[i]->config(a); return a; } void * pci_malloc(struct pci_access *a, int size) { void *x = malloc(size); if (!x) a->error("Out of memory (allocation of %d bytes failed)", size); return x; } void pci_mfree(void *x) { if (x) free(x); } static void pci_generic_error(char *msg, ...) { va_list args; va_start(args, msg); fputs("pcilib: ", stderr); vfprintf(stderr, msg, args); fputc('\n', stderr); exit(1); } static void pci_generic_warn(char *msg, ...) { va_list args; va_start(args, msg); fputs("pcilib: ", stderr); vfprintf(stderr, msg, args); fputc('\n', stderr); } static void pci_generic_debug(char *msg, ...) { va_list args; va_start(args, msg); vfprintf(stdout, msg, args); va_end(args); } static void pci_null_debug(char * UNUSED msg, ...) { } void pci_init(struct pci_access *a) { if (!a->error) a->error = pci_generic_error; if (!a->warning) a->warning = pci_generic_warn; if (!a->debug) a->debug = pci_generic_debug; if (!a->debugging) a->debug = pci_null_debug; if (a->method) { if (a->method >= PCI_ACCESS_MAX || !pci_methods[a->method]) a->error("This access method is not supported."); a->methods = pci_methods[a->method]; } else { unsigned int i; for(i=0; idebug("Trying method %d...", i); if (pci_methods[i]->detect(a)) { a->debug("...OK\n"); a->methods = pci_methods[i]; a->method = i; break; } a->debug("...No.\n"); } if (!a->methods) a->error("Cannot find any working access method."); } a->debug("Decided to use %s\n", a->methods->name); a->methods->init(a); } void pci_cleanup(struct pci_access *a) { struct pci_dev *d, *e; for(d=a->devices; d; d=e) { e = d->next; pci_free_dev(d); } if (a->methods) a->methods->cleanup(a); pci_free_name_list(a); pci_mfree(a); } void pci_scan_bus(struct pci_access *a) { a->methods->scan(a); } struct pci_dev * pci_alloc_dev(struct pci_access *a) { struct pci_dev *d = pci_malloc(a, sizeof(struct pci_dev)); bzero(d, sizeof(*d)); d->access = a; d->methods = a->methods; if (d->methods->init_dev) d->methods->init_dev(d); return d; } int pci_link_dev(struct pci_access *a, struct pci_dev *d) { d->next = a->devices; a->devices = d; return 1; } struct pci_dev * pci_get_dev(struct pci_access *a, int bus, int dev, int func) { struct pci_dev *d = pci_alloc_dev(a); d->bus = bus; d->dev = dev; d->func = func; return d; } void pci_free_dev(struct pci_dev *d) { if (d->methods->cleanup_dev) d->methods->cleanup_dev(d); pci_mfree(d); } static inline void pci_read_data(struct pci_dev *d, void *buf, int pos, int len) { if (pos & (len-1)) d->access->error("Unaligned read: pos=%02x, len=%d", pos, len); if (pos + len <= d->cache_len) memcpy(buf, d->cache + pos, len); else if (!d->methods->read(d, pos, buf, len)) memset(buf, 0xff, len); } byte pci_read_byte(struct pci_dev *d, int pos) { byte buf; pci_read_data(d, &buf, pos, 1); return buf; } word pci_read_word(struct pci_dev *d, int pos) { word buf; pci_read_data(d, &buf, pos, 2); return le16_to_cpu(buf); } u32 pci_read_long(struct pci_dev *d, int pos) { u32 buf; pci_read_data(d, &buf, pos, 4); return le32_to_cpu(buf); } int pci_read_block(struct pci_dev *d, int pos, byte *buf, int len) { return d->methods->read(d, pos, buf, len); } static inline int pci_write_data(struct pci_dev *d, void *buf, int pos, int len) { if (pos & (len-1)) d->access->error("Unaligned write: pos=%02x,len=%d", pos, len); if (pos + len <= d->cache_len) memcpy(d->cache + pos, buf, len); return d->methods->write(d, pos, buf, len); } int pci_write_byte(struct pci_dev *d, int pos, byte data) { return pci_write_data(d, &data, pos, 1); } int pci_write_word(struct pci_dev *d, int pos, word data) { word buf = cpu_to_le16(data); return pci_write_data(d, &buf, pos, 2); } int pci_write_long(struct pci_dev *d, int pos, u32 data) { u32 buf = cpu_to_le32(data); return pci_write_data(d, &buf, pos, 4); } int pci_write_block(struct pci_dev *d, int pos, byte *buf, int len) { if (pos < d->cache_len) { int l = (pos + len >= d->cache_len) ? (d->cache_len - pos) : len; memcpy(d->cache + pos, buf, l); } return d->methods->write(d, pos, buf, len); } void pci_fill_info(struct pci_dev *d, int flags) { if (flags & PCI_FILL_RESCAN) { flags &= ~PCI_FILL_RESCAN; d->known_fields = 0; } if (flags & ~d->known_fields) d->methods->fill_info(d, flags & ~d->known_fields); d->known_fields |= flags; } void pci_setup_cache(struct pci_dev *d, byte *cache, int len) { d->cache = cache; d->cache_len = len; } ltmodem-0.0.5/lib/dump.c100644 1750 144 5127 6652164605 12552 0ustar users/* * $Id: dump.c,v 1.1 1999/01/22 21:05:20 mj Exp $ * * The PCI Library -- Reading of Bus Dumps * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include #include #include "internal.h" static int dump_detect(struct pci_access *a) { return !!a->method_params[PCI_ACCESS_DUMP]; } static void dump_init(struct pci_access *a) { char *name = a->method_params[PCI_ACCESS_DUMP]; FILE *f; char buf[256]; struct pci_dev *dev = NULL; int len, bn, dn, fn, i, j; if (!a) a->error("dump: File name not given."); if (!(f = fopen(name, "r"))) a->error("dump: Cannot open %s: %s", name, strerror(errno)); while (fgets(buf, sizeof(buf)-1, f)) { char *z = strchr(buf, '\n'); if (!z) a->error("dump: line too long or unterminated"); *z-- = 0; if (z >= buf && *z == '\r') *z-- = 0; len = z - buf + 1; if (len >= 8 && buf[2] == ':' && buf[5] == '.' && buf[7] == ' ' && sscanf(buf, "%x:%x.%d ", &bn, &dn, &fn) == 3) { dev = pci_get_dev(a, bn, dn, fn); dev->aux = pci_malloc(a, 256); memset(dev->aux, 0xff, 256); pci_link_dev(a, dev); } else if (!len) dev = NULL; else if (dev && len >= 51 && buf[2] == ':' && buf[3] == ' ' && sscanf(buf, "%x: ", &i) == 1) { z = buf+3; while (isspace(z[0]) && isxdigit(z[1]) && isxdigit(z[2])) { z++; if (sscanf(z, "%x", &j) != 1 || i >= 256) a->error("dump: Malformed line"); ((byte *) dev->aux)[i++] = j; z += 2; } } } } static void dump_cleanup(struct pci_access * UNUSED a) { } static void dump_scan(struct pci_access * UNUSED a) { } static int dump_read(struct pci_dev *d, int pos, byte *buf, int len) { if (!d->aux) { struct pci_dev *e = d->access->devices; while (e && (e->bus != d->bus || e->dev != d->dev || e->func != d->func)) e = e->next; if (e) d = e; else return 0; } memcpy(buf, (byte *) d->aux + pos, len); return 1; } static int dump_write(struct pci_dev * UNUSED d, int UNUSED pos, byte * UNUSED buf, int UNUSED len) { d->access->error("Writing to dump files is not supported."); return 0; } static void dump_cleanup_dev(struct pci_dev *d) { if (d->aux) { pci_mfree(d->aux); d->aux = NULL; } } struct pci_methods pm_dump = { "dump", NULL, /* config */ dump_detect, dump_init, dump_cleanup, dump_scan, pci_generic_fill_info, dump_read, dump_write, NULL, /* init_dev */ dump_cleanup_dev }; ltmodem-0.0.5/lib/configure100755 1750 144 2320 6711143552 13332 0ustar users#!/bin/sh echo -n "Configuring libpci for your system..." prefix=${1:-/usr} version=${2:-0.0} sys=`uname -s` rel=`uname -r` cpu=`uname -m | sed 's/^i.86$/i386/;s/^sun4u$/sparc64/'` echo "$sys/$cpu $rel" if [ "$sys" != Linux ] ; then echo "libpci currently supports only Linux" exit 1 fi echo -n "Looking for access methods..." c=config.h echo >$c "#define ARCH_`echo $cpu | tr 'a-z' 'A-Z'`" case $rel in 2.[1-9]*|[3-9]*) echo -n " proc" echo >>$c '#define HAVE_PM_LINUX_PROC' echo >>$c '#define HAVE_LINUX_BYTEORDER_H' echo >>$c '#define PATH_PROC_BUS_PCI "/proc/bus/pci"' ok=1 ;; esac case $cpu in i386) echo -n " i386-ports" echo >>$c '#define HAVE_PM_INTEL_CONF' ok=1 ;; alpha|sparc|sparc64) echo >>$c '#define HAVE_64BIT_ADDRESS' # echo -n " syscalls" # echo >>$c '#define HAVE_PM_SYSCALLS' # ok=1 ;; esac echo >>$c '#define HAVE_PM_DUMP' echo " dump" if [ -z "$ok" ] ; then echo "WARNING: No real configuration access method is available." fi echo >>$c "#define PATH_PCI_IDS \"$prefix/share/pci.ids\"" if [ -f header.h ] ; then echo >>$c '#define HAVE_OWN_HEADER_H' fi echo >>$c "#define PCILIB_VERSION \"$version\"" sed '/^#define [^ ]*$/!d;s/^#define \(.*\)/\1=1/' <$c >config.mk ltmodem-0.0.5/lib/filter.c100644 1750 144 4515 6652164607 13074 0ustar users/* * $Id: filter.c,v 1.1 1999/01/22 21:05:22 mj Exp $ * * Linux PCI Library -- Device Filtering * * Copyright (c) 1998--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include "internal.h" void pci_filter_init(struct pci_access * UNUSED a, struct pci_filter *f) { f->bus = f->slot = f->func = -1; f->vendor = f->device = -1; } /* Slot filter syntax: [[bus]:][slot][.[func]] */ char * pci_filter_parse_slot(struct pci_filter *f, char *str) { char *colon = strchr(str, ':'); char *dot = strchr((colon ? colon + 1 : str), '.'); char *mid = str; char *e; if (colon) { *colon++ = 0; mid = colon; if (str[0] && strcmp(str, "*")) { long int x = strtol(str, &e, 16); if ((e && *e) || (x < 0 || x >= 0xff)) return "Invalid bus number"; f->bus = x; } } if (dot) *dot++ = 0; if (mid[0] && strcmp(mid, "*")) { long int x = strtol(mid, &e, 16); if ((e && *e) || (x < 0 || x >= 0x1f)) return "Invalid slot number"; f->slot = x; } if (dot && dot[0] && strcmp(dot, "*")) { long int x = strtol(dot, &e, 16); if ((e && *e) || (x < 0 || x >= 7)) return "Invalid function number"; f->func = x; } return NULL; } /* ID filter syntax: [vendor]:[device] */ char * pci_filter_parse_id(struct pci_filter *f, char *str) { char *s, *e; if (!*str) return NULL; s = strchr(str, ':'); if (!s) return "':' expected"; *s++ = 0; if (str[0] && strcmp(str, "*")) { long int x = strtol(str, &e, 16); if ((e && *e) || (x < 0 || x >= 0xffff)) return "Invalid vendor ID"; f->vendor = x; } if (s[0] && strcmp(s, "*")) { long int x = strtol(s, &e, 16); if ((e && *e) || (x < 0 || x >= 0xffff)) return "Invalid device ID"; f->device = x; } return NULL; } int pci_filter_match(struct pci_filter *f, struct pci_dev *d) { if ((f->bus >= 0 && f->bus != d->bus) || (f->slot >= 0 && f->slot != d->dev) || (f->func >= 0 && f->func != d->func)) return 0; if (f->device >= 0 || f->vendor >= 0) { pci_fill_info(d, PCI_FILL_IDENT); if ((f->device >= 0 && f->device != d->device_id) || (f->vendor >= 0 && f->vendor != d->vendor_id)) return 0; } return 1; } ltmodem-0.0.5/lib/header.h100644 1750 144 33357 6711145002 13052 0ustar users/* * $Id: header.h,v 1.3 1999/04/26 19:46:02 mj Exp $ * * The PCI Library -- PCI Header Structure (extracted from ) * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ /* * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */ #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features */ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ #define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ #define PCI_REVISION_ID 0x08 /* Revision ID */ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ #define PCI_HEADER_TYPE 0x0e /* 8 bits */ #define PCI_HEADER_TYPE_NORMAL 0 #define PCI_HEADER_TYPE_BRIDGE 1 #define PCI_HEADER_TYPE_CARDBUS 2 #define PCI_BIST 0x0f /* 8 bits */ #define PCI_BIST_CODE_MASK 0x0f /* Return result */ #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ /* * Base addresses specify locations in memory or I/O space. * Decoded size can be determined by writing a value of * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ #define PCI_BASE_ADDRESS_SPACE_IO 0x01 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */ #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fL) #define PCI_BASE_ADDRESS_IO_MASK (~0x03L) /* bit 1 is reserved if address_space = 1 */ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c #define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ /* 0x35-0x3b are reserved */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ #define PCI_MIN_GNT 0x3e /* 8 bits */ #define PCI_MAX_LAT 0x3f /* 8 bits */ /* Header type 1 (PCI-to-PCI bridges) */ #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ #define PCI_IO_LIMIT 0x1d #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ #define PCI_IO_RANGE_TYPE_16 0x00 #define PCI_IO_RANGE_TYPE_32 0x01 #define PCI_IO_RANGE_MASK ~0x0f #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ #define PCI_MEMORY_LIMIT 0x22 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f #define PCI_MEMORY_RANGE_MASK ~0x0f #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ #define PCI_PREF_MEMORY_LIMIT 0x26 #define PCI_PREF_RANGE_TYPE_MASK 0x0f #define PCI_PREF_RANGE_TYPE_32 0x00 #define PCI_PREF_RANGE_TYPE_64 0x01 #define PCI_PREF_RANGE_MASK ~0x0f #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ #define PCI_PREF_LIMIT_UPPER32 0x2c #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ #define PCI_IO_LIMIT_UPPER16 0x32 /* 0x34-0x3b is reserved */ #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ /* 0x3c-0x3d are same as for htype 0 */ #define PCI_BRIDGE_CONTROL 0x3e #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ /* Header type 2 (CardBus bridges) */ /* 0x14-0x15 reserved */ #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ #define PCI_CB_MEMORY_BASE_0 0x1c #define PCI_CB_MEMORY_LIMIT_0 0x20 #define PCI_CB_MEMORY_BASE_1 0x24 #define PCI_CB_MEMORY_LIMIT_1 0x28 #define PCI_CB_IO_BASE_0 0x2c #define PCI_CB_IO_BASE_0_HI 0x2e #define PCI_CB_IO_LIMIT_0 0x30 #define PCI_CB_IO_LIMIT_0_HI 0x32 #define PCI_CB_IO_BASE_1 0x34 #define PCI_CB_IO_BASE_1_HI 0x36 #define PCI_CB_IO_LIMIT_1 0x38 #define PCI_CB_IO_LIMIT_1_HI 0x3a #define PCI_CB_IO_RANGE_MASK ~0x03 /* 0x3c-0x3d are same as for htype 0 */ #define PCI_CB_BRIDGE_CONTROL 0x3e #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ #define PCI_CB_BRIDGE_CTL_SERR 0x02 #define PCI_CB_BRIDGE_CTL_ISA 0x04 #define PCI_CB_BRIDGE_CTL_VGA 0x08 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 #define PCI_CB_SUBSYSTEM_ID 0x42 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ /* 0x48-0x7f reserved */ /* Capability lists */ #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 /* Power Management Registers */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ #define PCI_PM_DATA_REGISTER 7 /* (??) */ #define PCI_PM_SIZEOF 8 /* AGP registers */ #define PCI_AGP_VERSION 2 /* BCD version number */ #define PCI_AGP_RFU 3 /* Rest of capability flags */ #define PCI_AGP_STATUS 4 /* Status register */ #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ #define PCI_AGP_COMMAND 8 /* Control register */ #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded * in a single byte as follows: * * 7:3 = slot * 2:0 = function */ #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) #define PCI_FUNC(devfn) ((devfn) & 0x07) /* Device classes and subclasses */ #define PCI_CLASS_NOT_DEFINED 0x0000 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 #define PCI_BASE_CLASS_STORAGE 0x01 #define PCI_CLASS_STORAGE_SCSI 0x0100 #define PCI_CLASS_STORAGE_IDE 0x0101 #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 #define PCI_CLASS_NETWORK_ETHERNET 0x0200 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 #define PCI_CLASS_NETWORK_FDDI 0x0202 #define PCI_CLASS_NETWORK_ATM 0x0203 #define PCI_CLASS_NETWORK_OTHER 0x0280 #define PCI_BASE_CLASS_DISPLAY 0x03 #define PCI_CLASS_DISPLAY_VGA 0x0300 #define PCI_CLASS_DISPLAY_XGA 0x0301 #define PCI_CLASS_DISPLAY_OTHER 0x0380 #define PCI_BASE_CLASS_MULTIMEDIA 0x04 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 #define PCI_BASE_CLASS_MEMORY 0x05 #define PCI_CLASS_MEMORY_RAM 0x0500 #define PCI_CLASS_MEMORY_FLASH 0x0501 #define PCI_CLASS_MEMORY_OTHER 0x0580 #define PCI_BASE_CLASS_BRIDGE 0x06 #define PCI_CLASS_BRIDGE_HOST 0x0600 #define PCI_CLASS_BRIDGE_ISA 0x0601 #define PCI_CLASS_BRIDGE_EISA 0x0602 #define PCI_CLASS_BRIDGE_MC 0x0603 #define PCI_CLASS_BRIDGE_PCI 0x0604 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 #define PCI_CLASS_BRIDGE_NUBUS 0x0606 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 #define PCI_CLASS_BRIDGE_OTHER 0x0680 #define PCI_BASE_CLASS_COMMUNICATION 0x07 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 #define PCI_BASE_CLASS_SYSTEM 0x08 #define PCI_CLASS_SYSTEM_PIC 0x0800 #define PCI_CLASS_SYSTEM_DMA 0x0801 #define PCI_CLASS_SYSTEM_TIMER 0x0802 #define PCI_CLASS_SYSTEM_RTC 0x0803 #define PCI_CLASS_SYSTEM_OTHER 0x0880 #define PCI_BASE_CLASS_INPUT 0x09 #define PCI_CLASS_INPUT_KEYBOARD 0x0900 #define PCI_CLASS_INPUT_PEN 0x0901 #define PCI_CLASS_INPUT_MOUSE 0x0902 #define PCI_CLASS_INPUT_OTHER 0x0980 #define PCI_BASE_CLASS_DOCKING 0x0a #define PCI_CLASS_DOCKING_GENERIC 0x0a00 #define PCI_CLASS_DOCKING_OTHER 0x0a01 #define PCI_BASE_CLASS_PROCESSOR 0x0b #define PCI_CLASS_PROCESSOR_386 0x0b00 #define PCI_CLASS_PROCESSOR_486 0x0b01 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 #define PCI_CLASS_PROCESSOR_CO 0x0b40 #define PCI_BASE_CLASS_SERIAL 0x0c #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 #define PCI_CLASS_SERIAL_ACCESS 0x0c01 #define PCI_CLASS_SERIAL_SSA 0x0c02 #define PCI_CLASS_SERIAL_USB 0x0c03 #define PCI_CLASS_SERIAL_FIBER 0x0c04 #define PCI_CLASS_OTHERS 0xff /* Several ID's we need in the library */ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_VENDOR_ID_COMPAQ 0x0e11 ltmodem-0.0.5/lib/proc.c100644 1750 144 11475 6706431473 12573 0ustar users/* * $Id: proc.c,v 1.2 1999/04/18 19:08:12 mj Exp $ * * The PCI Library -- Configuration Access via /proc/bus/pci * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #define _GNU_SOURCE #include #include #include #include #include #include #include "internal.h" #include #if defined(__GLIBC__) && __GLIBC__ == 2 && __GLIBC_MINOR__ < 1 #include #endif /* * As libc doesn't support pread/pwrite yet, we have to call them directly * or use lseek/read/write instead. */ #if !(defined(__GLIBC__) && __GLIBC__ == 2 && __GLIBC_MINOR__ > 0) #if defined(__GLIBC__) && !(defined(__powerpc__) && __GLIBC__ == 2 && __GLIBC_MINOR__ == 0) #ifndef SYS_pread #define SYS_pread __NR_pread #endif static int pread(unsigned int fd, void *buf, size_t size, loff_t where) { return syscall(SYS_pread, fd, buf, size, where); } #ifndef SYS_pwrite #define SYS_pwrite __NR_pwrite #endif static int pwrite(unsigned int fd, void *buf, size_t size, loff_t where) { return syscall(SYS_pwrite, fd, buf, size, where); } #else static _syscall4(int, pread, unsigned int, fd, void *, buf, size_t, size, loff_t, where); static _syscall4(int, pwrite, unsigned int, fd, void *, buf, size_t, size, loff_t, where); #endif #endif static void proc_config(struct pci_access *a) { a->method_params[PCI_ACCESS_PROC_BUS_PCI] = PATH_PROC_BUS_PCI; } static int proc_detect(struct pci_access *a) { char *name = a->method_params[PCI_ACCESS_PROC_BUS_PCI]; if (access(name, R_OK)) { a->warning("Cannot open %s", name); return 0; } a->debug("...using %s", name); return 1; } static void proc_init(struct pci_access *a) { a->fd = -1; } static void proc_cleanup(struct pci_access *a) { if (a->fd >= 0) { close(a->fd); a->fd = -1; } } static void proc_scan(struct pci_access *a) { FILE *f; char buf[256]; if (snprintf(buf, sizeof(buf), "%s/devices", a->method_params[PCI_ACCESS_PROC_BUS_PCI]) == sizeof(buf)) a->error("File name too long"); f = fopen(buf, "r"); if (!f) a->error("Cannot open %s", buf); while (fgets(buf, sizeof(buf)-1, f)) { struct pci_dev *d = pci_alloc_dev(a); unsigned int dfn, vend; sscanf(buf, #ifdef HAVE_64BIT_ADDRESS "%x %x %x %llx %llx %llx %llx %llx %llx %llx", #else "%x %x %x %lx %lx %lx %lx %lx %lx %lx", #endif &dfn, &vend, &d->irq, &d->base_addr[0], &d->base_addr[1], &d->base_addr[2], &d->base_addr[3], &d->base_addr[4], &d->base_addr[5], &d->rom_base_addr); d->bus = dfn >> 8U; d->dev = PCI_SLOT(dfn & 0xff); d->func = PCI_FUNC(dfn & 0xff); d->vendor_id = vend >> 16U; d->device_id = vend & 0xffff; d->known_fields = a->buscentric ? PCI_FILL_IDENT : (PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE); pci_link_dev(a, d); } fclose(f); } static int proc_setup(struct pci_dev *d, int rw) { struct pci_access *a = d->access; if (a->cached_dev != d || a->fd_rw < rw) { char buf[256]; if (a->fd >= 0) close(a->fd); if (snprintf(buf, sizeof(buf), "%s/%02x/%02x.%d", a->method_params[PCI_ACCESS_PROC_BUS_PCI], d->bus, d->dev, d->func) == sizeof(buf)) a->error("File name too long"); a->fd_rw = a->writeable || rw; a->fd = open(buf, a->fd_rw ? O_RDWR : O_RDONLY); if (a->fd < 0) a->warning("Cannot open %s", buf); a->cached_dev = d; } return a->fd; } static int proc_read(struct pci_dev *d, int pos, byte *buf, int len) { int fd = proc_setup(d, 0); int res; if (fd < 0) return 0; res = pread(fd, buf, len, pos); if (res < 0) { d->access->warning("proc_read: read failed: %s", strerror(errno)); return 0; } else if (res != len) { d->access->warning("proc_read: tried to read %d bytes at %d, but got only %d", len, pos, res); return 0; } return 1; } static int proc_write(struct pci_dev *d, int pos, byte *buf, int len) { int fd = proc_setup(d, 1); int res; if (fd < 0) return 0; res = pwrite(fd, buf, len, pos); if (res < 0) { d->access->warning("proc_write: write failed: %s", strerror(errno)); return 0; } else if (res != len) { d->access->warning("proc_write: tried to write %d bytes at %d, but got only %d", len, pos, res); return 0; } return 1; } static void proc_cleanup_dev(struct pci_dev *d) { if (d->access->cached_dev == d) d->access->cached_dev = NULL; } struct pci_methods pm_linux_proc = { "/proc/bus/pci", proc_config, proc_detect, proc_init, proc_cleanup, proc_scan, pci_generic_fill_info, proc_read, proc_write, NULL, /* init_dev */ proc_cleanup_dev }; ltmodem-0.0.5/lib/i386-ports.c100644 1750 144 13227 6652164614 13463 0ustar users/* * $Id: i386-ports.c,v 1.1 1999/01/22 21:05:26 mj Exp $ * * The PCI Library -- Direct Configuration access via i386 Ports * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #ifdef __GLIBC__ #include #endif #include "internal.h" static int intel_iopl_set = -1; static int intel_setup_io(void) { if (intel_iopl_set < 0) intel_iopl_set = (iopl(3) < 0) ? 0 : 1; return intel_iopl_set; } static void conf12_init(struct pci_access *a) { if (!intel_setup_io()) a->error("You need to be root to have access to I/O ports."); } static void conf12_cleanup(struct pci_access * UNUSED a) { iopl(3); intel_iopl_set = -1; } /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test * whether bus 00 contains a host bridge (this is similar to checking * techniques used in XFree86, but ours should be more reliable since we * attempt to make use of direct access hints provided by the PCI BIOS). * * This should be close to trivial, but it isn't, because there are buggy * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. */ static int intel_sanity_check(struct pci_access *a, struct pci_methods *m) { struct pci_dev d; a->debug("...sanity check"); d.bus = 0; d.func = 0; for(d.dev = 0; d.dev < 32; d.dev++) { u16 class, vendor; if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) || m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) { a->debug("...outside the Asylum at 0/%02x/0", d.dev); return 1; } } a->debug("...insane"); return 0; } /* * Configuration type 1 */ #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3)) static int conf1_detect(struct pci_access *a) { unsigned int tmp; int res = 0; if (!intel_setup_io()) { a->debug("...no I/O permission"); return 0; } outb (0x01, 0xCFB); tmp = inl (0xCF8); outl (0x80000000, 0xCF8); if (inl (0xCF8) == 0x80000000) res = 1; outl (tmp, 0xCF8); if (res) res = intel_sanity_check(a, &pm_intel_conf1); return res; } static int conf1_read(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xcfc + (pos&3); outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) { case 1: buf[0] = inb(addr); break; case 2: ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); break; case 4: ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); break; default: return pci_generic_block_read(d, pos, buf, len); } return 1; } static int conf1_write(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xcfc + (pos&3); outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) { case 1: outb(buf[0], addr); break; case 2: outw(le16_to_cpu(((u16 *) buf)[0]), addr); break; case 4: outl(le32_to_cpu(((u32 *) buf)[0]), addr); break; default: return pci_generic_block_write(d, pos, buf, len); } return 1; } /* * Configuration type 2. Obsolete and brain-damaged, but existing. */ static int conf2_detect(struct pci_access *a) { if (!intel_setup_io()) { a->debug("...no I/O permission"); return 0; } /* This is ugly and tends to produce false positives. Beware. */ outb(0x00, 0xCFB); outb(0x00, 0xCF8); outb(0x00, 0xCFA); if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) return intel_sanity_check(a, &pm_intel_conf2); else return 0; } static int conf2_read(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xc000 | (d->dev << 8) | pos; if (d->dev >= 16) /* conf2 supports only 16 devices per bus */ return 0; outb((d->func << 1) | 0xf0, 0xcf8); outb(d->bus, 0xcfa); switch (len) { case 1: buf[0] = inb(addr); break; case 2: ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); break; case 4: ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); break; default: outb(0, 0xcf8); return pci_generic_block_read(d, pos, buf, len); } outb(0, 0xcf8); return 1; } static int conf2_write(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xc000 | (d->dev << 8) | pos; if (d->dev >= 16) d->access->error("conf2_write: only first 16 devices exist."); outb((d->func << 1) | 0xf0, 0xcf8); outb(d->bus, 0xcfa); switch (len) { case 1: outb(buf[0], addr); break; case 2: outw(le16_to_cpu(* (u16 *) buf), addr); break; case 4: outl(le32_to_cpu(* (u32 *) buf), addr); break; default: outb(0, 0xcf8); return pci_generic_block_write(d, pos, buf, len); } outb(0, 0xcf8); return 1; } struct pci_methods pm_intel_conf1 = { "Intel-conf1", NULL, /* config */ conf1_detect, conf12_init, conf12_cleanup, pci_generic_scan, pci_generic_fill_info, conf1_read, conf1_write, NULL, /* init_dev */ NULL /* cleanup_dev */ }; struct pci_methods pm_intel_conf2 = { "Intel-conf2", NULL, /* config */ conf2_detect, conf12_init, conf12_cleanup, pci_generic_scan, pci_generic_fill_info, conf2_read, conf2_write, NULL, /* init_dev */ NULL /* cleanup_dev */ }; ltmodem-0.0.5/lib/generic.c100644 1750 144 11136 6666333360 13237 0ustar users/* * $Id: generic.c,v 1.4 1999/02/28 20:23:10 mj Exp $ * * The PCI Library -- Generic Direct Access Functions * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include "internal.h" static void pci_generic_scan_bus(struct pci_access *a, byte *busmap, int bus) { int dev, multi, ht; struct pci_dev *t = pci_alloc_dev(a); a->debug("Scanning bus %02x for devices...\n", bus); if (busmap[bus]) { a->warning("Bus %02x seen twice (firmware bug). Ignored.", bus); return; } busmap[bus] = 1; t->bus = bus; for(dev=0; dev<32; dev++) { t->dev = dev; multi = 0; for(t->func=0; t->func<8; t->func++) { u32 vd = pci_read_long(t, PCI_VENDOR_ID); struct pci_dev *d; if (!vd || vd == 0xffffffff) break; ht = pci_read_byte(t, PCI_HEADER_TYPE); if (!t->func) multi = ht & 0x80; ht &= 0x7f; d = pci_alloc_dev(a); d->bus = t->bus; d->dev = t->dev; d->func = t->func; d->vendor_id = vd & 0xffff; d->device_id = vd >> 16U; d->known_fields = PCI_FILL_IDENT; d->hdrtype = ht; pci_link_dev(a, d); switch (ht) { case PCI_HEADER_TYPE_NORMAL: break; case PCI_HEADER_TYPE_BRIDGE: case PCI_HEADER_TYPE_CARDBUS: pci_generic_scan_bus(a, busmap, pci_read_byte(t, PCI_SECONDARY_BUS)); break; default: a->debug("Device %02x:%02x.%d has unknown header type %02x.\n", d->bus, d->dev, d->func, ht); } if (!multi) break; } } } void pci_generic_scan(struct pci_access *a) { byte busmap[256]; bzero(busmap, sizeof(busmap)); pci_generic_scan_bus(a, busmap, 0); } void pci_generic_fill_info(struct pci_dev *d, int flags) { struct pci_access *a = d->access; if (flags & PCI_FILL_IDENT) { d->vendor_id = pci_read_word(d, PCI_VENDOR_ID); d->device_id = pci_read_word(d, PCI_DEVICE_ID); } if (flags & PCI_FILL_IRQ) d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE); if (flags & PCI_FILL_BASES) { int cnt = 0, i; bzero(d->base_addr, sizeof(d->base_addr)); switch (d->hdrtype) { case PCI_HEADER_TYPE_NORMAL: cnt = 6; break; case PCI_HEADER_TYPE_BRIDGE: cnt = 2; break; case PCI_HEADER_TYPE_CARDBUS: cnt = 1; break; } if (cnt) { u16 cmd = pci_read_word(d, PCI_COMMAND); for(i=0; ibase_addr[i] = x; if (x & PCI_BASE_ADDRESS_SPACE_IO) { if (!a->buscentric && !(cmd & PCI_COMMAND_IO)) d->base_addr[i] = 0; } else if (a->buscentric || (cmd & PCI_COMMAND_MEMORY)) { if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) { if (i >= cnt-1) a->warning("%02x:%02x.%d: Invalid 64-bit address seen.", d->bus, d->dev, d->func); else { u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4); #ifdef HAVE_64BIT_ADDRESS d->base_addr[i-1] |= ((pciaddr_t) y) << 32; #else if (y) { a->warning("%02x:%02x.%d 64-bit device address ignored.", d->bus, d->dev, d->func); d->base_addr[i-1] = 0; } #endif } } } else d->base_addr[i] = 0; } } } if (flags & PCI_FILL_ROM_BASE) { int reg = 0; d->rom_base_addr = 0; switch (d->hdrtype) { case PCI_HEADER_TYPE_NORMAL: reg = PCI_ROM_ADDRESS; break; case PCI_HEADER_TYPE_BRIDGE: reg = PCI_ROM_ADDRESS1; break; } if (reg) { u32 a = pci_read_long(d, reg); if (a & PCI_ROM_ADDRESS_ENABLE) d->rom_base_addr = a; } } } static int pci_generic_block_op(struct pci_dev *d, int pos, byte *buf, int len, int (*r)(struct pci_dev *d, int pos, byte *buf, int len)) { if ((pos & 1) && len >= 1) { if (!r(d, pos, buf, 1)) return 0; pos++; buf++; len--; } if ((pos & 3) && len >= 2) { if (!r(d, pos, buf, 2)) return 0; pos += 2; buf += 2; len -= 2; } while (len >= 4) { if (!r(d, pos, buf, 4)) return 0; pos += 4; buf += 4; len -= 4; } if (len >= 2) { if (!r(d, pos, buf, 2)) return 0; pos += 2; buf += 2; len -= 2; } if (len && !r(d, pos, buf, 1)) return 0; return 1; } int pci_generic_block_read(struct pci_dev *d, int pos, byte *buf, int len) { return pci_generic_block_op(d, pos, buf, len, d->access->methods->read); } int pci_generic_block_write(struct pci_dev *d, int pos, byte *buf, int len) { return pci_generic_block_op(d, pos, buf, len, d->access->methods->write); } ltmodem-0.0.5/lib/syscalls.c100644 1750 144 1554 6652164633 13443 0ustar users/* * $Id: syscalls.c,v 1.1 1999/01/22 21:05:42 mj Exp $ * * The PCI Library -- Configuration Access via Syscalls * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "internal.h" static int sysc_detect(struct pci_access *a) { return 0; } static void sysc_init(struct pci_access *a) { } static void sysc_cleanup(struct pci_access *a) { } static int sysc_read(struct pci_dev *d, int pos, byte *buf, int len) { return 0; } static int sysc_write(struct pci_dev *d, int pos, byte *buf, int len) { return 0; } struct pci_methods pm_syscalls = { "syscalls", NULL, /* config */ sysc_detect, sysc_init, sysc_cleanup, pci_generic_scan, pci_generic_fill_info, sysc_read, sysc_write, NULL, /* init_dev */ NULL /* cleanup_dev */ }; ltmodem-0.0.5/ltmodem.c100444 0 0 51456 6755677211 13112 0ustar rootroot/* * $Id: ltmodem.c,v 1.4 1999/08/16 02:59:21 root Exp $ * * Lucent PCI modem diagnostics tool. * * Copyright (c) 1999 Richard J.M. Close * Copyright (c) 1999 Pavel Machek * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "ltmodem.h" unsigned int portbase; unsigned int modem_irq; int verbose = 0; /* Main program. */ int main(int argc, char **argv) { char c; sync(); /* it's for your own protection */ setvbuf(stdout, NULL, _IONBF, 0); puts("ltmodem version " LTMODEM_VERSION); modem = 0; io_cnt = 0; pacc = pci_alloc(); pacc->error = die; pci_filter_init(pacc, &filter); pci_init(pacc); scan_devices(); sort_them(); /* If modem is found then it sets modem_dev to device structure for modem, and modem =1 */ if ( !find_modem() ) { printf ("Sorry, no Lucent PCI modem that I know of was found.\n"); printf ("If you have one fitted then please mail me with the details\n"); printf ("at: richard@close.u-net.com please include an output from\n"); printf ("cat /proc/pci and as much info. on the card as possible.\n"); exit(1); } while ((c = getopt(argc, argv, "imovth" )) != -1) { switch(c) { case 'i': show_modem(); main_menu(); break; case 't': show_modem(); setup_irq(); io_init(); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x7e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0xff); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x00); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x25); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x89); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); break; case 'o': show_modem(); setup_irq(); io_init(); //dp_offhook_cmd(); /* go_offhook(); -- seems to do something slightly different */ #if 0 while(1) { printf( "%4x %4x %4x %4x %4x %4x\n", readbio(0x1002), readbio(0x1120), readbio(0xffff), readbio(0xf0ff), readbio(0xf1ff), readbio(0xf2ff)); sleep(1); } #endif break; case 'm': continous_monitoring(3, 1000); break; case 'v': verbose++; break; case 'h': default: printf( "Usage: ltmodem [-imovt]\n" ); printf( "-i interative use.\n-m monitoring ports/registers.\n"); printf( "-o run offhook command.\n-v increase level of verbosity.\n"); printf( "-t mess around with mercury gain (whatever that is). \n"); goto exit; } } exit: pci_cleanup(pacc); return 0; } void setup_irq(void) { printf( "Removing i2sig\n" ); system("rmmod i2sig"); // Setup IRQ variable used by other stuff. modem_irq = modem_dev->dev->irq; #if 0 char buf[10240]; sprintf( buf, "insmod ./i2sig.o irq=%d pid=%d", modem_irq, getpid()); printf( "Installing new i2sig: %s\n", buf ); system(buf); #endif signal_init(); } /* Find any known any Lucent modems. */ static int find_modem(void) { struct device *d; int i; for(d=first_dev; d; d=d->next) { struct pci_dev *p = d->dev; /* Only cards with vendor ID = Lucent!. */ if (p->vendor_id == 0x11c1) { modem_dev = d; modem = 1; io_cnt = 0; /* Record I/O addresses. */ for(i=0; ibase_addr[i]; u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (flg == 0xffffffff) flg = 0; if (!pos && !flg) continue; if (flg & PCI_BASE_ADDRESS_SPACE_IO) { io_address[i] = pos & PCI_BASE_ADDRESS_IO_MASK; io_length[i] = (io_address[i] < 0x3f8) ? 8 : 256; io_cnt = i; } } } } return modem; } // Show any found modem. static void show_modem(void) { int c; struct pci_dev *p = modem_dev->dev; byte classbuf[128], devbuf[128]; unsigned int irq = p->irq; byte latency = get_conf_byte( modem_dev, PCI_LATENCY_TIMER); word status = get_conf_word( modem_dev, PCI_STATUS); word cmd = get_conf_word( modem_dev, PCI_COMMAND); byte max_lat, min_gnt; word subsys_v, subsys_d; char ssnamebuf[256]; printf("%02x:%02x.%x %s: %s", p->bus, p->dev, p->func, pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word( modem_dev, PCI_CLASS_DEVICE), 0), pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id)); if (c = get_conf_byte( modem_dev, PCI_REVISION_ID)) printf(" (rev %02x)", c); if (c = get_conf_byte( modem_dev, PCI_CLASS_PROG)) printf(" (prog-if %02x)", c); putchar('\n'); max_lat = get_conf_byte( modem_dev, PCI_MAX_LAT); min_gnt = get_conf_byte( modem_dev, PCI_MIN_GNT); subsys_v = get_conf_word( modem_dev, PCI_SUBSYSTEM_VENDOR_ID); subsys_d = get_conf_word( modem_dev, PCI_SUBSYSTEM_ID); if (subsys_v && subsys_v != 0xffff) printf("\tSubsystem: %s\n", pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, subsys_v, subsys_d)); printf("\tFlags: "); if (cmd & PCI_COMMAND_MASTER) printf("bus master, "); if (cmd & PCI_COMMAND_VGA_PALETTE) printf("VGA palette snoop, "); if (cmd & PCI_COMMAND_WAIT) printf("stepping, "); if (cmd & PCI_COMMAND_FAST_BACK) printf("fast Back2Back, "); if (status & PCI_STATUS_66MHZ) printf("66Mhz, "); if (status & PCI_STATUS_UDF) printf("user-definable features, "); printf("%s devsel", ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" : ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" : ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??"); if (cmd & PCI_COMMAND_MASTER) printf(", latency %d", latency); if (irq) printf(", IRQ " IRQ_FORMAT, irq); putchar('\n'); show_htype0( modem_dev); } // Modem monitoring functions. void monitor_modem(void) { // Value input by user. char input = 'z'; // Monitoring activity type: // registers = 1, I/O = 2. int monitor_type = 1; // Monitoring period in milliseconds, defaults to one second. int monitoring_interval = 1000; while (input != 'Q') { // Ignore the newline char. if (input != '\n') { printf ("***************************************************\n"); printf ("monitoring menu (Monitor monitorIo monitorRegs monitorBoth iNterval Quit): "); } // Get user input in uppercase. input = toupper (getchar()); switch (input) { case 'M': continous_monitoring(monitor_type, monitoring_interval); break; case 'I': printf( "Will monitor I/O ports.\n" ); monitor_type = 2; break; case 'R': printf( "Will monitor PCI registers.\n" ); monitor_type = 1; break; case 'B': printf( "Will monitor I/O ports and PCI registers.\n" ); monitor_type = 3; break; case 'N': monitoring_interval = set_monitoring_interval(); break; case '\n': break; case 'Q': break; default: printf ("Illegal option: %c\n", input); } } } int set_monitoring_interval(void){ // Value input by user. int input = 0; char trash; // Allow user to set interval. printf ("Set monitoring interval (in miliseconds): "); scanf ("%d%c", &input, &trash); if (input > 0) { // Return the user's value. printf ("Interval set to %d milliseconds.\n", input); return input; } else { // Default to one second. printf ("Illegal interval, using 1 second default.\n"); return 1000; } } void continous_monitoring(int monitor_type, int monitoring_interval){ // Iteration loop variable. unsigned int i; // Main monitoring loop. while (1) { // Monitor registers or I/O depending on current setting. if (monitor_type & 1) { // Re-scan device. pci_scan_bus(pacc); modem_dev = scan_device(modem_dev->dev); // Show the hex. show_hex_dump(modem_dev); } if (monitor_type & 2) { // Get access to all of I/O space. if (iopl(3) < 0) { perror("ltmodem: iopl()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Read the ports. printf("I/O ports\n "); // Loop for each known port. for (i=1;i<=io_cnt;i++) { unsigned int j; printf( "%x: ", io_address[i] ); for (j=0; jdev); /* Show the hex. */ show_hex_dump(modem_dev); } void set_modem_cont_reg(void) { /* value input by user. */ int input = 0; /* CR input after first char. */ char trash; /* Allow user to set control register. */ printf ("Set control register (value in hex): "); scanf ("%x%c", &input, &trash); printf ("Writing %x to control register.\n", input); /* command register is at address 04. */ pci_write_word(modem_dev->dev, 0x04, input); } void set_modem_io(void) { unsigned int i; /* value input by user. */ unsigned int input = 0; unsigned int offset = 0; /* CR input after first char. */ char trash; if (io_cnt > 0) { printf("I/O ports found:\n"); for(i=1; i<=io_cnt; i++){ printf("%d - I/O port at %x.\n", i, io_address[i]); } // Select the port. printf ("Port to write long word at (in hex): "); scanf ("%x%c", &input, &trash); // Write the value. if ((input > 0) && (input <= io_cnt)) { // Allow user to write to selected I/O port. i = input; printf ("Write to %x, enter value (in hex): ", io_address[i]); scanf ("%x%c", &input, &trash); // Get offset to use. printf ("Offset to use (in hex): "); scanf ("%x%c", &offset, &trash); printf ("Writing %2x to I/O port %x + %x.\n", input, io_address[i], offset); // Write value to port. WRITE_PORT_UCHAR ((io_address[i] + offset), input); ///* Delay 10ms. */ usleep(10000); /* Read back the port. */ printf("Read back value: %2x.\n", READ_PORT_UCHAR(io_address[i] + offset)); } } } /* Main command menu. */ void main_menu(void) { /* char input by user. */ char input = 'z'; while (input != 'Q') { // Ignore the newline char. if (input != '\n') { printf ("main menu (Monitor Write Quit): "); } // Get user input in uppercase. input = toupper (getchar()); switch (input) { case 'M': monitor_modem(); break; case 'W': set_modem(); break; case '\n': break; case 'Q': break; default: printf ("Illegal option: %c\n", input); } } /* Bye bye... */ printf ("User stopped ltmodem.\n"); } /******************************************************************************** * * PCI utilities. * *********************************************************************************/ static struct device * scan_device(struct pci_dev *p) { int how_much = 0x40; /* First 64 bytes. */ struct device *d; if (!pci_filter_match(&filter, p)) return NULL; d = xmalloc(sizeof(struct device)); bzero(d, sizeof(*d)); d->dev = p; if (!pci_read_block(p, 0, d->config, how_much)) die("Unable to read %d bytes of configuration space.", how_much); if (how_much < 128 && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS) { /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */ if (!pci_read_block(p, 0, d->config+64, 64)) die("Unable to read cardbus bridge extension data."); how_much = 128; } d->config_cnt = how_much; pci_setup_cache(p, d->config, d->config_cnt); pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE); return d; } static void scan_devices(void) { struct device *d; struct pci_dev *p; pci_scan_bus(pacc); for(p=pacc->devices; p; p=p->next) if (d = scan_device(p)) { d->next = first_dev; first_dev = d; } } static int check_root(void) { static int is_root = -1; if (is_root < 0) is_root = !geteuid(); return is_root; } static int config_fetch(struct device *d, unsigned int pos, unsigned int len) { if (pos + len < d->config_cnt) return 1; if (pacc->method != PCI_ACCESS_DUMP && !check_root()) return 0; return pci_read_block(d->dev, pos, d->config + pos, len); } /* Config space accesses */ static inline byte get_conf_byte(struct device *d, unsigned int pos) { return d->config[pos]; } static word get_conf_word(struct device *d, unsigned int pos) { return d->config[pos] | (d->config[pos+1] << 8); } static u32 get_conf_long(struct device *d, unsigned int pos) { return d->config[pos] | (d->config[pos+1] << 8) | (d->config[pos+2] << 16) | (d->config[pos+3] << 24); } /* Sorting */ static int compare_them(const void *A, const void *B) { const struct pci_dev *a = (*(const struct device **)A)->dev; const struct pci_dev *b = (*(const struct device **)B)->dev; if (a->bus < b->bus) return -1; if (a->bus > b->bus) return 1; if (a->dev < b->dev) return -1; if (a->dev > b->dev) return 1; if (a->func < b->func) return -1; if (a->func > b->func) return 1; return 0; } static void sort_them(void) { struct device **index, **h, **last_dev; int cnt; struct device *d; cnt = 0; for(d=first_dev; d; d=d->next) cnt++; h = index = alloca(sizeof(struct device *) * cnt); for(d=first_dev; d; d=d->next) *h++ = d; qsort(index, cnt, sizeof(struct device *), compare_them); last_dev = &first_dev; h = index; while (cnt--) { *last_dev = *h; last_dev = &(*h)->next; h++; } *last_dev = NULL; } /* Normal output */ static void show_bases(struct device *d, int cnt) { struct pci_dev *p = d->dev; word cmd = get_conf_word(d, PCI_COMMAND); int i; for(i=0; ibase_addr[i]; u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (flg == 0xffffffff) flg = 0; if (!pos && !flg) continue; printf("\tRegion %d: ", i); if (pos && !flg) /* Reported by the OS, but not by the device */ { printf("[virtual] "); flg = pos; } if (flg & PCI_BASE_ADDRESS_SPACE_IO) { pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK; printf("I/O ports at "); if (a) { portbase = (unsigned int) a; printf(IO_FORMAT, a); } else if (flg & PCI_BASE_ADDRESS_IO_MASK) printf(""); else printf(""); if (!(cmd & PCI_COMMAND_IO)) printf(" [disabled]"); } else { int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK; pciaddr_t a = pos & PCI_ADDR_MEM_MASK; int done = 0; u32 z = 0; printf("Memory at "); if (t == PCI_BASE_ADDRESS_MEM_TYPE_64) { if (i >= cnt - 1) { printf("\n"); done = 1; } else { i++; z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (buscentric_view) { if (a || z) printf("%08x" ADDR_FORMAT, z, a); else printf(""); done = 1; } } } if (!done) { if (a) printf(ADDR_FORMAT, a); else printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "" : ""); } printf(" (%s, %sprefetchable)", (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" : (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" : (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3", (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); if (!(cmd & PCI_COMMAND_MEMORY)) printf(" [disabled]"); } putchar('\n'); } } static void show_htype0(struct device *d) { unsigned long rom = d->dev->rom_base_addr; show_bases(d, htype0_cnt); if (rom & 1) printf("\tExpansion ROM at %08lx%s\n", rom & PCI_ROM_ADDRESS_MASK, (rom & PCI_ROM_ADDRESS_ENABLE) ? "" : " [disabled]"); if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) { int where = get_conf_byte(d, PCI_CAPABILITY_LIST); while (where) { int id, next, cap; printf("\tCapabilities: "); if (!config_fetch(d, where, 4)) { puts(""); break; } id = get_conf_byte(d, where + PCI_CAP_LIST_ID); next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT); cap = get_conf_word(d, where + PCI_CAP_FLAGS); printf("[%02x] ", where); if (id == 0xff) { printf("\n"); break; } switch (id) { case PCI_CAP_ID_PM: printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); break; case PCI_CAP_ID_AGP: break; default: printf("#%02x [%04x]", id, cap); } where = next; } } } static struct bus * find_bus(struct bridge *b, unsigned int n) { struct bus *bus; for(bus=b->first_bus; bus; bus=bus->sibling) if (bus->number == n) break; return bus; } static struct bus * new_bus(struct bridge *b, unsigned int n) { struct bus *bus = xmalloc(sizeof(struct bus)); bus = xmalloc(sizeof(struct bus)); bus->number = n; bus->sibling = b->first_bus; bus->first_dev = NULL; bus->last_dev = &bus->first_dev; b->first_bus = bus; return bus; } static void insert_dev(struct device *d, struct bridge *b) { struct pci_dev *p = d->dev; struct bus *bus; if (! (bus = find_bus(b, p->bus))) { struct bridge *c; for(c=b->child; c; c=c->next) if (c->secondary <= p->bus && p->bus <= c->subordinate) return insert_dev(d, c); bus = new_bus(b, p->bus); } /* Simple insertion at the end _does_ guarantee the correct order as the * original device list was sorted by (bus, devfn) lexicographically * and all devices on the new list have the same bus number. */ *bus->last_dev = d; bus->last_dev = &d->next; d->next = NULL; } /* Bus mapping mode */ static void do_map_bridges(int bus, int min, int max) { struct bus_info *bi = bus_info + bus; struct bus_bridge *b; bi->guestbook = 1; for(b=bi->bridges; b; b=b->next) { if (bus_info[b->first].guestbook) b->bug = 1; else if (b->first < min || b->last > max) b->bug = 2; else { bus_info[b->first].via = b; do_map_bridges(b->first, b->first, b->last); } } } /* Show hexadecimal dump of first 64 bytes of the PCI configuration space (the standard header). Useful for debugging of drivers and lspci itself. */ static void show_hex_dump(struct device *d) { unsigned int i; printf("Command reg: "); printf(" %02x", get_conf_byte(d, 5)); printf(" %02x", get_conf_byte(d, 4)); putchar('\t'); printf("Status reg: "); printf(" %02x", get_conf_byte(d, 7)); printf(" %02x", get_conf_byte(d, 6)); putchar('\n'); /* Note! the byte order is lsb msb */ printf("Base address regs: "); for(i=0x10; i<0x24; i++){ printf(" %02x", get_conf_byte(d, i)); } putchar('\n'); } // Lucent modem specific stuff. void dp_onhook_cmd(void) { #if 0 printf( "Should call cell_onhook()\n" ); dp_modem_command(0x13, 0, 0); x_output( 7); x_output(0x0e); x_output(0x14); x_output(0x10); if (byte_59ED2 == 0) { x_output(0x19); x_output( 3); x_output(0x12); } else byte_59ED2 = 0x0a; dp_write_dsp_ram(0xf20, 0x42f8); dp_regwrite(0xd8, 0xff); dp_regwrite(0xb7, 0xff); /* dp_tad_downloaded = dp_fax_downloaded = 0; */ if (byte_59ED4 == 1) { byte_59ED4 = 0; byte_59EB2 = 0; } v8bis_app_reset(); dp_init_local_phone_state(); V34Mode = 0; dp_update_diagnostics(); if (x_status != 0) goto l2D1; x_status = 1; ll_save_diagnostics(); l2D1: if (byte_59ED2 != 0) goto l2E7; if (x_modem_mode == 3) goto l2E7; dp_run_rom(); l2E7: dp_first_call = 0; #endif } void go_onhook(void) { dp_onhook_cmd(); } void io_init(void) { struct pci_dev *p = modem_dev->dev; bool bMarsChipset; /* Only cards with device ID 044? are mars chipset based. */ bMarsChipset = ((p->device_id & 0xfff0) == 0x0440); // Set up the port IO. port_io_init(io_address[1], io_address[2], bMarsChipset); } ltmodem-0.0.5/irq.c100644 0 0 410 6755152316 12160 0ustar rootroot#include "irq.h" void signal_handler(int i) { printf( "Signal came in with %d.\n", i); signal(SIGUSR1, signal_handler); dp_dsp_isr(); sleep(1); } void signal_init(void) { printf( "Signal handler installed\n" ); signal(SIGUSR1, signal_handler); } ltmodem-0.0.5/portIO.c100644 0 0 56240 6755707734 12667 0ustar rootroot/* * Port IO routines + emulation of low level layers from ltmodem.sys. * * Copyright 1999 Pavel Machek and R.J.M. Close, distribute under GPL */ #include "portIO.h" // IO port subroutines etc. // The first section has routines based on the NT HAL library calls. // The implementation in this file is not a copy of the real code but // has the same interface and is designed to be used by user space processes. // A version for a device driver will be implemented at a later date, this // will be much simpler as more system resources are available to drivers. // Low level interface //========================================================================================== // // The following section contains routines that have been "reverse engineered" from those in // in the NT driver code. The functions are named according to thier names in original // lucent .sys driver. // Port variables - these are initialised by port_io_init. The values below are purely // for illustration purposes. // PCIOutAddr holds a (?) base port address and PCIInAddr has this base + 4. unsigned int PCIOutAddr = 0x6200; unsigned int PCIInAddr = 0x6204; // I think this initial value is wrong. I need to find out how this is being set. // In read_Blacktip_Resource it is set to 118h, 110h, 108h, or 100h. This may be a clue! // dp_run_rom sets it to 260h. unsigned int BaseAddress =0x6300; unsigned int BaseAddress2 = 0x6300; unsigned int ComAddress = 0; unsigned int word_59ED7 = 0; // Set up in dp_board_enable with values derived from BaseAddress, ComAddress and word_59ED7. unsigned int BaseAddressIndex = 0; unsigned int BaseAddressData = 0; unsigned char BaseValue = 0; volatile unsigned char dp_byte_f, dp_byte_e, dp_byte_d, dp_byte_c; volatile unsigned int dp_bamil_rd7, dp_bamil_rbc, dp_dsp_data_in_progress, dp_sleep, CpqFlag = 0, dp_state; bool x_dsp_mars = false; int dp_cmd_timer; unsigned char byte_59F18 = 0, byte_59EF3 = 0x12, byte_59EF4 = 0x50; unsigned int x_chip_version = 0, dp_version; unsigned char byte_59F30 = 0x88, byte_59F31 = 0x80, byte_59F32 = 0x6B, byte_59F33 = 0x1E; /* Mercury */ unsigned char byte_59E96 = 2, byte_59E97 = 1, byte_59F0B = 0x82, byte_59F04 = 2 /* or maybe 0? */, byte_59F2D = 0, byte_59F2E = 0; int dp_dialing_status = 0, dp_timer = 0, x_modem_mode = 0, x_status = 0; // Assume inactive for now. unsigned char cell_active = 0; // DSP RAM read fail count. What happens if this is >255 ? unsigned char dp_readram_failcnt = 0; void Init_Mars(void) { Write_mdm_byte(0x37, 0x22); Write_mdm_byte(0x30, 1); Write_mdm_byte(0x3c, 0xff); Write_mdm_byte(0x3e, 1); } void port_io_init(unsigned int Portbase1, unsigned int Portbase2, bool IsMarsChipset) { char chipMessage[3]; // Set the mars chipset flag. x_dsp_mars = IsMarsChipset; // Which portbase do we use? Pavel used the second so ... portbase = Portbase2; if (IsMarsChipset) strcpy(chipMessage, "a"); else strcpy(chipMessage, "no"); printf( "Initialising with ports at %x and %x, with %s mars chipset detected.\n", Portbase1, Portbase2, chipMessage ); printf( "Assuming portbase at %x\n", portbase ); // Set up other portbases. PCIOutAddr = Portbase1; PCIInAddr = Portbase1 + 4; if (iopl(3) < 0) { perror("portIO: iopl(3) failed"); fprintf(stderr, "This program must be run as root.\n"); } printf( "Initializing modem\n" ); dp_init_modem(); printf( "Modem init done\n" ); } // Places args in a long word to go to port, then reads back. unsigned int PciRead_dword (unsigned char arg1, unsigned char arg2, unsigned char arg3) { unsigned int ecx; unsigned char al; // shl al, 03h (al = arg1). shift 3 left, ie. mult by 8. // and cl, 07h (cl = arg3). mask off all but last 3 bits. // or al, cl OR the results. al = (arg1 * 8) | (arg3 & 7); //xor ecx, ecx -> ecx = 0 ! //mov ch, al set byte 1 to above result. //mov cl , byte ptr [ esp + 8 ] ecx = (256 * al) + arg2; // put second arg in byte0. // or ecx , 080000000h Set most sig bit. ecx = ecx | 0x80000000; WRITE_PORT_ULONG (PCIOutAddr, ecx); return (READ_PORT_ULONG (PCIInAddr)); // ret 0Ch ;0x00025425 : c20c00 wind esp back 12 bytes. } unsigned int PciRead_word (unsigned char arg1, unsigned char arg2, unsigned char arg3) { unsigned int dataOut; unsigned short readPort; dataOut = (256 * (arg1 * 8) | (arg3 & 7)) + arg3; dataOut = dataOut | 0x80000000; WRITE_PORT_ULONG (PCIOutAddr, dataOut); readPort = PCIInAddr | (arg2 & 2); return (READ_PORT_USHORT (readPort)); } void PciWrite_dword (unsigned int arg1, unsigned int arg2, unsigned int* ptrValue) { unsigned int eax, ecx, Value; ecx = arg1 * 2084; // shl ecx, 0xBh ecx = ecx & 0x0000ffff; //movzx ecx, cx eax = arg2 & 0xFF; eax = eax | ecx; eax = eax | 0x80000000; WRITE_PORT_ULONG (PCIOutAddr, eax); Value = *ptrValue; WRITE_PORT_ULONG (PCIInAddr, Value); } // Place value in port (base address in BaseAddress) plus offset. void Write_mdm_byte (unsigned int portOffset, unsigned char value) { WRITE_PORT_UCHAR ((BaseAddress + portOffset), value); } // Place value in port (base address in BaseAddress) plus offset. void Write_mdm_word (unsigned int portOffset, unsigned short value) { WRITE_PORT_USHORT ((BaseAddress + portOffset), value); } void dp_out_port (int arg) /* ??? This looks like having no args in disassembly */ { WRITE_PORT_UCHAR (BaseAddressIndex, BaseValue); WRITE_PORT_UCHAR (BaseAddressData, arg); } int dp_in_port(void) { WRITE_PORT_UCHAR (BaseAddressIndex, BaseValue); return READ_PORT_UCHAR (BaseAddressData); } void dp_regwrite (unsigned char val, unsigned int port) { BaseValue = val; BaseAddressIndex = BaseAddress; dp_out_port(port); } int dp_regread (unsigned int port) { BaseValue = port; if (port <= 0x7f) { BaseAddressIndex = BaseAddress; return dp_in_port(); } if (port < 0xa0) { BaseAddressIndex = BaseAddress2; return dp_in_port(); } if (port <= 0xcf) { BaseAddressIndex = BaseAddress; return dp_in_port(); } BaseAddressIndex = BaseAddress2; return dp_in_port(); } void dp_int_regwrite(unsigned int port, unsigned int val) { WRITE_PORT_UCHAR(BaseAddress, port); WRITE_PORT_UCHAR(BaseAddressData, val); } int dp_int_regread(unsigned int port) { if (port <= 0x7f) { WRITE_PORT_UCHAR(BaseAddress, port); return READ_PORT_UCHAR(BaseAddressData); } if (port < 0xa0) { WRITE_PORT_UCHAR(BaseAddress + 2, port); return READ_PORT_UCHAR(BaseAddressData); } if (port <= 0xcf) { WRITE_PORT_UCHAR(BaseAddress, port); return READ_PORT_UCHAR(BaseAddressData); } WRITE_PORT_UCHAR(BaseAddress + 2, port); return READ_PORT_UCHAR(BaseAddressData); } int dp_dsp_regread (unsigned int arg) { dp_byte_f = 0; dp_regwrite(0xD8, 0x18); dp_regwrite(0x36, arg); dp_regwrite(0x37, 0x06); dp_cmd_timer = x_current_time(); while(1) { if (!dp_byte_f) { if (x_elapsed_time(dp_cmd_timer) < 0xc8) continue; } if (dp_byte_f != 2) { dp_regwrite(0xD8, 0xFF); dp_byte_e = 0; } return dp_byte_e; } } int dp_read_dsp_ram(int where) { dp_byte_f = 0; dp_regwrite(0xd8, 0x18); dp_regwrite(0x34, where); dp_regwrite(0x35, (where & 0xff00) / 256); dp_regwrite(0x37, 4); dp_cmd_timer = x_current_time(); do { if (dp_byte_f != 0) break; } while (x_elapsed_time(dp_cmd_timer) < 0xc8); if (dp_byte_f != 1) { dp_regwrite(0xd8, 0xff); dp_byte_e = 0; dp_byte_d = 0; if (x_dsp_mars) Write_mdm_word(0x3c, 0x1ff); // Increment fail count. dp_readram_failcnt++; } else // Clear fail count. dp_readram_failcnt = 0; return ((dp_byte_e * 256) + dp_byte_d); } void dp_write_dsp_ram(int addr, int val) { dp_regwrite(0xd8, 0x18); dp_regwrite(0x32, val & 0xff); dp_regwrite(0x33, (val>>8) & 0xff); dp_regwrite(0x34, addr & 0xff); dp_regwrite(0x35, (addr>>8) & 0xff); dp_regwrite(0x37, 1); wait_for_core_read(); } void dp_modem_command (unsigned int a0, unsigned int a4, unsigned int a8) { if (a0 != 0x0c) { if (!(dp_dsp_regread(0xB5) && 1)) dp_regread(0xB0); /* 2EC73 */ if (!(dp_dsp_regread(0xB5) && 0x10)) { dp_regwrite(0xB6, 0xEF); dp_dsp_regread(0xB0); dp_regwrite(0xB0, 0); } /* 2EC9B */ dp_regwrite(0xB7, 0xFF); dp_regwrite(0xB6, 0xEE); dp_bamil_rd7 = 0xF3; dp_regwrite(0xD7, 0xF3); dp_dsp_data_in_progress = 0; } dp_regwrite(0xD8, 0x18); dp_regwrite(0x35, a8); dp_regwrite(0x36, a4); dp_regwrite(0x37, a0); return wait_for_core_read(); } void dp_modem_command_long(int a0, int a4, int a8, int aC, int a10) { dp_regwrite(0xD8, 0x18); dp_regwrite(0x33, a10); dp_regwrite(0x34, aC); dp_regwrite(0x35, a8); dp_regwrite(0x36, a4); dp_regwrite(0x37, a0); return wait_for_core_read(); } void x_output_init(void) { if (x_dsp_mars) { dp_regwrite(0xb8, 1); dp_regwrite(0xb9, 1); dp_regwrite(0xba, 0x40); dp_regwrite(0xbb, 0x40); dp_regwrite(0xdb, 0x41); dp_regwrite(0xdc, 0); } else { dp_regwrite(0xb8, 0xe0); dp_regwrite(0xb9, 0xc0); dp_regwrite(0xba, 0x80); dp_regwrite(0xbb, 0x80); dp_regwrite(0xdb, 0); dp_regwrite(0xdc, 0); } } void x_output(int arg) { unsigned int ebx = 1; if (arg>0x2c) return; switch(arg) { // 0002EAF0 off_2EAF0 dd offset loc_2E71C 0 case 0: x_output_init(); //set_boardid(); //x_set_hardware_options(); break; // 0002EAF8 dd offset loc_2E73A case 1: dp_modem_command(0x11, 0, 0); return; // 0002EAFC dd offset loc_2E740 2 case 2: dp_modem_command(0x12, 0, 0); return; // 0002EB00 dd offset loc_2EAEA case 3: case 4: case 5: return; // 0002EB0C dd offset loc_2E706 6 // 0002EB10 dd offset loc_2E6F8 // 0002EB14 dd offset loc_2E7DC 8 case 8: if (!x_dsp_mars) die( "implement me: 2e7e6\n" ); dp_write_dsp_ram(0x0d, 0x40); return; // 0002EB18 dd offset loc_2E7B8 9 // 0002EB1C dd offset off_2E7B1 10 case 10: /* something _very_ strange */ /* 0x68, 0x30, 0x01, 0x00, (nop?!), */ dp_write_dsp_ram(0x0d, 0x130); return; // 0002EB20 dd offset off_2E7AA 11 // 0002EB24 dd offset loc_2E74E 12 // 0002EB28 dd offset loc_2E77E 13 // 0002EB2C dd offset loc_2E9E4 14 case 14: if (!byte_59F0B) return; if (!CpqFlag) return; if (x_dsp_mars) { writebio(0x304, 0); return; } writebio(0x80, 0); return; // 0002EB30 dd offset loc_2EA07 15 /* Similar to 14 with minor difference! (, 1 -> , 0) */ case 15: if (!byte_59F0B) return; if (!CpqFlag) return; if (x_dsp_mars) { writebio(0x304, 1); return; } writebio(0x80, 1); return; // 0002EB34 dd offset loc_2EA34 16 // 0002EB38 dd offset loc_2EA55 17 case 17: writebio(0xffff, 1); if (CpqFlag == (ebx & 0xff)) return; // loc_2EABC: writebio(0x302, ebx & 0xff); return; case 18: case 19: case 20: case 21: return; // 0002EB4C dd offset loc_2E807 22 // 0002EB50 dd offset loc_2E89B // 0002EB54 dd offset loc_2EACF 24 // 0002EB58 dd offset loc_2EAC3 // 0002EB5C dd offset loc_2EA72 // 0002EB60 dd offset loc_2EA7C 27 // 0002EB64 dd offset loc_2EA8D case 28: if (!x_dsp_mars) writebio(0x308, ebx); else writebio(0x304, ebx); return; // 0002EB68 dd offset loc_2EA97 29 /* (hmm, like 28 but use ", 0" instead */ // 0002EB6C dd offset loc_2EAA8 case 30: if (!x_dsp_mars) writebio(0xffff, ebx); else writebio(0x308, ebx); return; // 0002EB70 dd offset loc_2EAB2 31 case 32: case 33: case 36: case 37: return; // 0002EB7C dd offset loc_2E9BA 34 // 0002EB80 dd offset loc_2E9BD 35 // 0002EB8C dd offset loc_2E9C8 38 // 0002EB90 dd offset loc_2E9CB // 0002EB94 dd offset loc_2E9D9 // 0002EB98 dd offset loc_2E9D6 // 0002EB9C dd offset loc_2E964 42 // 0002EBA0 dd offset loc_2E99D default: die( "x_output: %d - not implemented\n", arg ); } } int x_input(int arg) { unsigned char al; switch (arg) { case 0x38: // loc_2E6A2 needs completing. if (x_dsp_mars) al = readbio(0x1120); else al = readbio(0xffff); break; case 0x39: // loc_2E67D break; case 0x3e: // loc_2E671 break; case 0x40: // loc_2E667 die( "x_input: 0x%x - not implemented\n", arg ); break; case 0x41: if (cell_active == 1) return 0; // loc_2E6D1 if (!x_dsp_mars) { al = readbio(0x1140); if (al != 0) { al = readbio(0x1140); return 0; } else { // loc_2E6D7 return 1; } } else { al = readbio(0x1110); if (!al) return 1; readbio(0x1110); return 0; } default: /* 6d1 */ } printf( "x_input: unimplemented %x\n", arg ); return 0; } //======================================================================== // // void go_offhook(void) /* Ouch, is it real command for going offhook? It looks like it is used only in some tests! */ { printf( "Going offhook..." ); x_output(0x13); x_output(0x11); x_output(0x02); dp_state = 0x14; printf( "ok\n" ); } void dp_board_enable (void) { if (CpqFlag == 1) { if (ComAddress == BaseAddress) { if ((word_59ED7 != 0xCCB0) && (word_59ED7 != 0xCDB0)) BaseAddress = 0xEC; else BaseAddress = 0xBC; } else if ((BaseAddress != 0xEC) && (BaseAddress != 0xBC)) BaseAddress = BaseAddress & 0xFFF8; } x_chip_version = 0; BaseAddressIndex = BaseAddress; // ToshibaFlag = 1; // I don't think so! x_dsp_mars = 1; // Mmm? depends on device ID. BaseAddressData = BaseAddress + 1; BaseAddress2 = BaseAddress + 2; Init_Mars(); dp_regwrite (0xCB, 8); if (x_dsp_mars == 1) return; // I think my card has a mars chipset so this stuff // probably doesn't matter (yet). //dp_dsp_regread_poll(6, 0xC0, 2); // etc... } int dp_init_modem(void) { dp_dsp_data_in_progress = 0; dp_sleep = 0; printf( "Enabling board\n" ); dp_board_enable(); dp_regwrite(0xd8, 0xff); dp_regwrite(0xd7, 0xff); dp_regwrite(0xcb, 8); printf( "Sending commands" ); dp_modem_command(0x13, 0, 0); printf( "." ); dp_modem_command(0x12, 0, 0); printf( "." ); dp_modem_command_long(0x29, 0xff, 1, 0x87, 0); printf( ":" ); dp_bamil_rbc |= 0xff; dp_regwrite(0xbc, 0xff); dp_regwrite(0xbd, 0xff); dp_regwrite(0xbd, 0); dp_regwrite(0xbe, 0); dp_regwrite(0xb7, 0xff); dp_regwrite(0xd8, 0xff); dp_regwrite(0xb6, 0xee); dp_bamil_rd7 = 0xf3; dp_regwrite(0xd7, 0xf3); x_sleep(0x64); printf( "." ); dp_modem_command(0x13, 0, 0); printf( "." ); dp_modem_command(0x2d, 0, 0); printf( "." ); dp_modem_command_long(0x2e, 1, 0x23, 7, 0); printf( "." ); dp_modem_command(0x13, 0, 0); printf( "\n" ); dp_byte_f = 0; dp_read_dsp_ram(0x3a); dp_read_dsp_ram(0x3a); if (dp_byte_f != 1) { printf( "Init: read_dsp_ram did not set dsp_byte_f\n" ); return 0; } printf( "\nRom checksum is %x.\n", dp_dsp_rom_checksum() ); /* some code looking around rom checksums */ if (x_dsp_mars) { int version; version = dp_dsp_regread(0x0b); printf( "\nChip version is %x (mars).\n", version ); x_chip_version = version>>6; if (x_chip_version) { dp_regwrite(0xa0, 0x21); dp_regwrite(0xa4, 0); } } x_output(0); { int shift = (byte_59F18 != 0); dp_write_dsp_ram(0x40, byte_59EF3 >> shift); dp_write_dsp_ram(0x41, byte_59EF4 >> shift); } dp_write_dsp_ram(0x43, 2); if ((!x_chip_version) && (!x_dsp_mars)) { /* ... */ } /* ... */ if (x_dsp_mars == 1) dp_modem_command_long(3, 0xc0, 0, 8, 0); /* dp_tad_downloaded = dp_fax_downloaded = 0; dp_init_local_phone_timer(); dp_first_call = 1; */ dp_set_mercury_gain(); printf( "Modem init complete\n" ); return 1; } void process_ring(void) { printf( "Ring came?!\n" ); #if 0 dp_int_regwrite(0xd8, 0xff); if (dp_ring_int_count > 1) { dp_bamil_rd7 = 2; dp_ring_int = 1; // init_local_phone_timer(); return; } dp_ring_int_count++; if ((dp_sleep == 1) && (dp_ring_int_count == 1)) dp_regwrite(0xCB, 8); x_wakeup(); #endif } void process_v34(void) { printf( "Process v34?\n" ); #if 0 if (!(dp_int_regread(0xb6) & 0x10)) goto lE07; if (byte_59ECB != 1) goto lE02; if (V34Mode != 0) goto lE02; io_dual_port_rx(); goto lE07; lE02: dual_port_rx(); lE07: if (dp_int_regread(0xb6) & 1) dual_port_tx(); #endif } int dp_dsp_isr(void) { int i, todo; // edi = 0xd7 i = dp_int_regread(0xd7); todo = i & 0xff; if ((!todo) || (todo == 0xff)) goto failexit; printf( "[irq %x]", todo ); if (x_dsp_mars == 1) Write_mdm_word(0x3c, 0x101); dp_int_regwrite(0xd7, 0xff); // esi = 0xd8 if (todo & 2) process_ring(); if (todo & 8) { dp_int_regwrite(0xD8, 8); dp_byte_c = dp_int_regread(0x32); dp_byte_d = dp_int_regread(0x33); dp_byte_e = dp_int_regread(0x34); dp_byte_f = dp_int_regread(0x35); } if (todo & 4) process_v34(); if (todo & 0x40) { int i; i = dp_int_regread(0xbc); // esi = 0xbd dp_int_regwrite(0xbd, i); dp_int_regwrite(0xbd, ~i); /* they used not on lower byte only */ if (i & 0x18) { printf( "What do you want to do with cellphone?\n" ); #if 0 cell_isr(); x_wakeup(); #endif } } /* E52 */ dp_int_regwrite(0xd7, dp_bamil_rd7); WRITE_PORT_UCHAR(BaseAddressIndex, BaseValue); return 1; failexit: WRITE_PORT_UCHAR(BaseAddressIndex, BaseValue); return 0; } /* Ugly, feel free to rewrite it to be really readable. But I do not care - this function is not critical in any way */ int dp_dsp_rom_checksum(void) { int i; dp_byte_f = 0; dp_modem_command(0x10, 0, 0); l94E: if (dp_byte_f == 5) goto l972; i = x_elapsed_time(dp_cmd_timer); if (i<64) goto l94E; if (dp_byte_f != 5) goto l987; l972: dp_version = dp_byte_e << 8 | dp_byte_d; goto l98E; l987: dp_version = 0; l98E: dp_byte_f = 0; dp_modem_command(0x14, 0, 0); l99D: if (dp_byte_f == 3) goto l9C1; i = x_elapsed_time(dp_cmd_timer); if (i < 0xc8) goto l99D; if (dp_byte_f != 3) goto l9CA; l9C1: return dp_read_dsp_ram(0x49); l9CA: printf( "Returning zero, checksum failed?\n" ); return 0; } int dp_change_mercury_gain(int a0, int a4, int a8, int aC) { int res; printf( "Change mercury gain: %x, %x, %x, %x =", a0, a4, a8, aC ); dp_regwrite(0x32, aC); dp_modem_command_long(0x2f, 1, a0, a4, a8); res = dp_read_dsp_ram(0x3a); printf( "%x\n", res ); return res; } void dp_set_mercury_gain(void) { dp_change_mercury_gain(byte_59F30, byte_59F31, byte_59F32, byte_59F33); } int readbio(int arg) { int var, res; if ((arg & 0xf00) == 0xf00) return 0; if ((arg & 0xf00) == 0x100) var = 0xbb; else { if ((arg & 0xf00) == 0x200) var = 0xdc; else var = 0xb9; } res = dp_regread(var) & arg; printf( "[readbio: %x]", res ); return res; } void writebio(int val, int strange) { int ebx = val; int addr; printf( "writebio(%x, %x)\n", val, strange); #if 0 if ((val & 0xff) > 0x80) return; #endif val = (val & 0xffffff00) | 0xb9; if ((val & 0xf00) != 0x100) goto l482; val = (val & 0xffffff00) | 0xbb; l441: addr = val & 0xff; if (strange == 1) { if (!(val & 0x1000)) goto l457; } if ((strange != 0) || (!(val & 0x1000))) { strange = dp_regread(addr) & ((~ebx) & 0xff); dp_regwrite(addr, strange); return; } l457: strange = dp_regread(addr) | (ebx & 0xff); dp_regwrite(addr, strange); return; l482: if ((val & 0xf00) == 0x200) { val = (val & 0xffffff00) | 0xdc; goto l441; } if ((val & 0xf00) != 0x300) goto l441; writebiom(ebx, strange); return; } void writebiom(int val, int strange) { int al; al = val & 0x0f; if ((strange == 1) && (!(val & 0x1000))) goto do_and; if ((strange) || (!(val & 0x1000))) { byte_59F33 &= ~al; dp_set_mercury_gain(); return; } do_and: byte_59F33 |= al; dp_set_mercury_gain(); return; } unsigned char dp_offhook_cmd(void) { int esi; #if 0 if (cell_active) { ... } dp_timer = x_current_time(); if (dp_ring_detected()) { ... } #endif /* 2CFB8 */ if (byte_59E97) { switch (byte_59E96) { case 3: x_output(0x0b); break; case 2: x_output(0x0a); break; default: x_output(0x09); break; } dp_modem_command(0x13, 0, 0); x_output(0x08); } x_output(0x0e); x_output(0x11); x_output(0x02); if (byte_59F0B != 0xff) x_output(0x0f); if (((byte_59F04 != 0) && (dp_dialing_status == 0))) { x_output(0x1c); x_output(0x1e); dp_timer = x_current_time(); esi = x_current_time(); while (1) { if (x_elapsed_time(esi)>0x0a) break; if (!x_input(0x41)) continue; esi = dp_timer = x_current_time(); if (x_elapsed_time(esi) < 0x50 /* strange_table_lookup()*/ ) continue; x_output(0x03); /* x_send_mail(7, 1, 0, 0); */ return 0; } /* 0A6 */ if (byte_59F2E) x_output(0x1b); if (byte_59F2D) x_output(0x1d); } if ((x_modem_mode != 2) && (x_modem_mode != 3)) { x_output(0x13); /* at_init_diagnostics(); */ x_status = 0; } else { x_output(0x14); if (CpqFlag == 1) x_output(0x0d); } /* 0FE */ if (byte_59F0B == 0xff) { /* dp_init_local_phone_timer(); */ return 1; } dp_timer = x_current_time(); /* Ouch, another strange table lookup */ #if 0 if (maybe) x_output(0x10); #endif return 1; } //================================================================= // Fake functions! void expect_irq(void) { dp_dsp_isr(); } //================================================================= // Time functions. unsigned int x_current_time(void) { // Returns the number of milliseconds since boot up. // Machine code takes number of ticks (100nS apart) // and multiplies them by 10000 to get the numer of milliseconds. // open /proc/uptime for reading. Hard coded file name! ;) FILE* fpUptime = fopen("/proc/uptime", "r"); if (fpUptime != NULL) { // Read values from file. double uptime, idletime; fscanf (fpUptime, "%lf %lf", &uptime, &idletime); // Close file. fclose(fpUptime); // Convert float value of seconds to milliseconds. return (unsigned int) (uptime * 1000) + 3; } else { // Failure. fprintf(stderr, "ltmodem: could not open /proc/uptime for reading.\n"); return 0; } } int x_elapsed_time(unsigned int from) { expect_irq(); // Why ? (not in machine code?) // uses eax - ecx so result must be 32 bit. return (x_current_time() - from); //return (time(NULL)-from) * 0x70; } void x_sleep(int howlong) { expect_irq(); usleep(howlong * 1000); expect_irq(); } void wait_for_core_read(void) { x_sleep(100); } ltmodem-0.0.5/portIO.h100644 0 0 5431 6755203252 12632 0ustar rootroot#ifndef PORTIO_H #define PORTIO_H 1 #include #include #include "pciutils.h" #include "HAL.h" #include "stdbool.h" // IO port subroutines etc. // // These routines have been "reverse engineered" from those in in the NT driver code, ltmodem.sys. void Init_Mars(void); // Maybe use an object for the modem I/O properties? // Called by main routine which passes the base addres of the I/O ports. void port_io_init(unsigned int Portbase1, unsigned int Portbase2, bool IsMarsChipset); unsigned int portbase; // Places args in a long word to go to port, then reads back. unsigned int PciRead_dword (unsigned char arg1, unsigned char arg2, unsigned char arg3); unsigned int PciRead_word (unsigned char arg1, unsigned char arg2, unsigned char arg3); void PciWrite_dword (unsigned int arg1, unsigned int arg2, unsigned int* ptrValue); // Place value in port (base address in BaseAddress) plus offset. void Write_mdm_byte (unsigned int portOffset, unsigned char value); // Place value in port (base address in BaseAddress) plus offset. void Write_mdm_word (unsigned int portOffset, unsigned short value); // ??? This looks like having no args in disassembly. void dp_out_port (int arg); int dp_in_port(void); void dp_regwrite (unsigned char val, unsigned int port); int dp_regread (unsigned int port); void dp_int_regwrite(unsigned int port, unsigned int val); int dp_int_regread(unsigned int port); int dp_dsp_regread (unsigned int arg); int dp_read_dsp_ram(int where); void dp_write_dsp_ram(int addr, int val); void dp_modem_command (unsigned int a0, unsigned int a4, unsigned int a8); void dp_modem_command_long(int a0, int a4, int a8, int aC, int a10); //======================================================================== // X stuff! void x_output_init(void); void x_output(int arg); int x_input(int arg); //======================================================================== // // void go_offhook(void); /* Ouch, is it real command for going offhook? It looks like it is used only in some tests! */ void dp_board_enable(void); int dp_init_modem(void); void process_ring(void); void process_v34(void); int dp_dsp_isr(void); /* Ugly, feel free to rewrite it to be really readable. But I do not care - this function is not critical in any way */ int dp_dsp_rom_checksum(void); int dp_change_mercury_gain(int a0, int a4, int a8, int aC); void dp_set_mercury_gain(void); int readbio(int arg); void writebio(int val, int strange); void writebiom(int val, int strange); unsigned char dp_offhook_cmd(void); //================================================================= // Fake functions! void expect_irq(void); unsigned int x_current_time(void); int x_elapsed_time(unsigned int from); void x_sleep(int howlong); void wait_for_core_read(void); #endif /* PORTIO_H */ ltmodem-0.0.5/pci.ids100644 1750 144 135670 6737324010 12206 0ustar users# # List of PCI ID's # # Maintained by Martin Mares # If you have any new entries, send them to the maintainer. # # $Id: pci.ids,v 1.26 1999/05/19 12:01:31 mj Exp $ # # Vendors and devices. Please keep sorted. 0000 Gammagraphx, Inc. 001a Ascend Communications, Inc. 003d Lockheed Martin-Marietta Corp 0e11 Compaq Computer Corporation 3032 QVision 1280/p Rev 0 3033 QVision 1280/p Rev 1 3034 QVision 1280/p Rev 2 4000 4000 [Triflex] ae10 Smart-2/P RAID Controller ae29 MIS-L ae2a MPC ae2b MIS-E ae32 Netelligent 10/100 ae34 Netelligent 10 ae35 Integrated NetFlex-3/P ae40 Netelligent 10/100 Dual ae43 ProLiant Integrated Netelligent 10/100 ae69 CETUS-L ae6c Northstar b011 Integrated Netelligent 10/100 b012 Netelligent 10 T/2 b030 Netelligent WS 5100 f130 NetFlex-3/P ThunderLAN 1.0 f150 NetFlex-3/P ThunderLAN 2.3 1000 Symbios Logic Inc. (formerly NCR) 0001 53c810 0002 53c820 0003 53c825 0004 53c815 0005 53c810AP 0006 53c860 000b 53c896 000c 53c895 000d 53c885 000f 53c875 008f 53c875J 0701 83C885 gigabit ethernet 0702 Yellowfin G-NIC gigabit ethernet 0901 61C102 1000 63C815 1002 ATI Technologies Inc 4158 68800AX [Mach32] 4354 215CT [Mach64 CT] 4358 210888CX [Mach64 CX] 4554 210888ET [Mach64 ET] 4742 215GB [Mach64 GB] 4744 215GD [Mach64 GD] 4749 215GI [Mach64 GI] 4750 215GP [Mach64 GP] 4751 215GQ [Mach64 GQ] 4754 215GT [Mach64 GT] 4755 215GTB [Mach64 GTB] 4756 215IIC [Mach64 GT IIC] 4758 210888GX [Mach64 GX] 4c47 215LG [Mach64 LG] 4c54 264LT [Mach64 LT] 5654 264VT [Mach64 VT] 5655 264VTB [Mach64 VTB] 5656 264VT4 [Mach64 VT4] 1003 ULSI Systems 0201 US201 1004 VLSI Technology Inc 0005 82C592-FC1 0006 82C593-FC1 0007 82C594-AFC2 0008 82C596/7 [Wildcat] 0009 82C597-AFC2 000c 82C541 [Lynx] 000d 82C543 [Lynx] 0101 82C532 0102 82C534 0103 82C538 0104 82C535 0105 82C147 0200 82C975 0280 82C925 0702 VAS96011 [Golden Gate II] 1005 Avance Logic, Inc. 2301 ALG2301 2302 ALG2302 2364 ALG2364 1006 Reply Group 1007 NetFrame Systems Inc 1008 Epson 100a Phoenix Technologies 100b National Semiconductor Corporation 0001 DP83810 0002 87415 d001 87410 100c Tseng Labs Inc 3202 ET4000/W32p rev A 3205 ET4000/W32p rev B 3206 ET4000/W32p rev C 3207 ET4000/W32p rev D 3208 ET6000 100d AST Research Inc 100e Weitek 9001 P9000 9100 P9100 1010 Video Logic, Ltd. 1011 Digital Equipment Corporation 0001 DECchip 21050 0002 DECchip 21040 [Tulip] 0004 DECchip 21030 [TGA] 0007 NVRAM [Zephyr NVRAM] 0008 KZPSA [KZPSA] 0009 DECchip 21140 [FasterNet] 000d PBXGB [TGA2] 000f DEFPA 0014 DECchip 21041 [Tulip Pass 3] 0016 DGLPB [OPPO] 0019 DECchip 21142/43 0021 DECchip 21052 0022 DECchip 21150 0024 DECchip 21152 0025 DECchip 21153 0026 DECchip 21154 1012 Micronics Computers Inc 1013 Cirrus Logic 0038 GD 7548 00a0 GD 5430/40 [Alpine] 00a4 GD 5434-4 [Alpine] 00a8 GD 5434-8 [Alpine] 00ac GD 5436 [Alpine] 00b8 GD 5446 00bc GD 5480 00d0 GD 5462 00d4 GD 5464 [Laguna] 00d6 GD 5465 [Laguna] 1100 CL 6729 1110 PD 6832 1200 GD 7542 [Nordic] 1202 GD 7543 [Viking] 1204 GD 7541 [Nordic Light] 6001 CS 4610 6003 CS 4614 1014 IBM 000a Fire Coral 0018 TR 001b GXT-150P 001d 82G2675 0020 MCA 0022 IBM27-82351 002d Python 002e ServeRAID controller 0036 Miami 003e TR_Wake 0046 MPIC interrupt controller 007d 3780IDSP [MWave] ffff MPIC-2 interrupt controller 1015 LSI Logic Corp of Canada 1016 ICL Personal Systems 1017 SPEA Software AG 1018 Unisys Systems 1019 Elitegroup Computer Systems 101a AT&T GIS (NCR) 0005 100VG ethernet 101b Vitesse Semiconductor 101c Western Digital 0193 33C193A 0197 33C197A 0296 33C296A 3193 7193 3197 WD 7197 3296 33C296A 4296 34C296 c24a 90C 101e American Megatrends Inc. 9010 MegaRAID 101f PictureTel 1020 Hitachi Computer Products 1021 OKI Electric Industry Co. Ltd. 1022 Advanced Micro Devices 2000 79c970 [PCnet LANCE] 2001 79c978 [HomePNA] 2020 53c974 [PCscsi] 2040 79c974 1023 Trident Microsystems 2000 4DWave DX 2001 4DWave NX 9320 TGUI 9320 9397 Cyber9397 9420 TGUI 9420 9430 TGUI 9430 9440 TGUI 9440 9660 TGUI 9660/9680/9682 9750 3DIm`age 975 1024 Zenith Data Systems 1025 Acer Incorporated 1435 M1435 1445 M1445 1449 M1449 1451 M1451 1461 M1461 3141 M3141 3143 M3143 3145 M3145 3147 M3147 3149 M3149 3151 M3151 1028 Dell Computer Corporation 1029 Siemens Nixdorf IS 102a LSI Logic 0000 HYDRA 0010 ASPEN 102b Matrox Graphics, Inc. 0010 MGA-I [Impression] 0518 MGA-II [Athena] 0519 MGA 2064W [Millennium] 051a MGA 1064SG [Mystique] 051b MGA 2164W [Millennium II] 051e MGA 1064SG AGP [Mystique AGP] 051f MGA 2164W AGP [Millennium II AGP] 0520 MGA G200 PCI 0521 MGA G200 AGP [Millennium AGP] 0d10 MGA Ultima/Impression 1000 MGA G100 [Productiva] 1001 MGA G100 [Productiva AGP] 102c Chips and Technologies 00b8 64310 00d8 65545 00dc 65548 00e0 65550 00e4 65554 00e5 65555 102d Wyse Technology Inc. 102e Olivetti Advanced Technology 102f Toshiba America 1030 TMC Research 1031 Miro Computer Products AG 5601 DC20 ASIC 1033 NEC Corporation 0035 USB 0046 PowerVR PCX2 [midas] 1034 Framatome Connectors USA Inc. 1035 Comp. & Comm. Research Lab 1036 Future Domain Corp. 0000 TMC-18C30 [36C70] 1037 Hitachi Micro Systems 1038 AMP, Inc 1039 Silicon Integrated Systems 0001 5591/5592 AGP 0002 SG86C202 0008 85C503 0009 ACPI 0200 5597/5598 VGA 0204 82C204 0205 SG86C205 0406 85C501/2 0496 85C496 0597 5513C 0601 85C601 5107 5107 5511 5511/5512 5513 5513 5571 5571 5591 5591/5592 Host 5597 5597 [SiS5582] 6236 6236 AGP 7001 7001 103a Seiko Epson Corporation 103b Tatung Co. of America 103c Hewlett-Packard Company 1030 J2585A 1031 J2585B 2910 E2910A 2925 E2925A 103e Solliday Engineering 103f Synopsys/Logic Modeling Group 1040 Accelgraphics Inc. 1041 Computrend 1042 Micron 1000 FDC 37C665 1001 37C922 3000 Samurai_0 3010 Samurai_1 3020 Samurai_IDE 1043 Asustek Computer, Inc. 1044 Distributed Processing Technology 1012 Domino RAID Engine a400 SmartCache/Raid I-IV Controller a500 PCI Bridge a501 SmartRAID V Controller 1045 OPTi Inc. c178 92C178 c557 82C557 [Viper-M] c558 82C558 [Viper-M ISA+IDE] c621 82C621 c700 82C700 c701 82C701 [FireStar Plus] c814 82C814 [Firebridge 1] c822 82C822 c824 82C824 c861 82C861 d568 82C825 [Firebridge 2] 1046 IPC Corporation, Ltd. 1047 Genoa Systems Corp 1048 Elsa AG 1000 QuickStep 1000pro 1049 Fountain Technologies, Inc. 104a SGS Thomson Microelectronics 0008 STG 2000X 0009 STG 1764X 104b BusLogic 0140 BT-946C (old) [multimaster 01] 1040 BT-946C (BA80C30) [MultiMaster 10] 8130 Flashpoint LT 104c Texas Instruments 3d04 TVP4010 [Permedia] 3d07 TVP4020 [Permedia 2] a001 TDC1570 a100 TDC1561 ac10 PCI1050 ac11 PCI1053 ac12 PCI1130 ac13 PCI1031 ac15 PCI1131 ac16 PCI-1250 ac17 PCI-1220 104d Sony Corporation 104e Oak Technology, Inc 0107 OTI107 104f Co-time Computer Ltd 1050 Winbond Electronics Corp 0840 89C840 0940 89C940 1051 Anigma, Inc. 1053 Young Micro Systems 1054 Hitachi, Ltd 1055 EFAR Microsystems 1056 ICL # Motorola made a mistake and used this value, please duplicate Moto # entries here -- Cort 1507 Motorola Computer Group 0001 MPC105 [Eagle] 0002 MPC106 [Grackle] 4801 Raven 4802 Falcon 4803 Hawk 4806 CPX8216 1057 Motorola Computer Group 0001 MPC105 [Eagle] 0002 MPC106 [Grackle] 4801 Raven 4802 Falcon 4803 Hawk 4806 CPX8216 1058 Electronics & Telecommunications RSH 1059 Teknor Industrial Computers Inc 105a Promise Technology, Inc. 4d33 20246 4d38 20262 5300 DC5300 105b Foxconn International, Inc. 105c Wipro Infotech Limited 105d Number 9 Computer Company 2309 Imagine 128 2339 Imagine 128-II 493d Imagine 128 T2R [Ticket to Ride] 105e Vtech Computers Ltd 105f Infotronic America Inc 1060 United Microelectronics 0001 UM82C881 0002 UM82C886 0101 UM8673F 0881 UM8881 0886 UM8886F 0891 UM8891A 1001 UM886A 673a UM8886BF 8710 UM8710 886a UM8886A 8881 UM8881F 8886 UM8886F 888a UM8886A 8891 UM8891A 9017 UM9017F e881 UM8881N e886 UM8886N e891 UM8891N 1061 I.I.T. 0001 AGX016 0002 IIT3204/3501 1062 Maspar Computer Corp 1063 Ocean Office Automation 1064 Alcatel CIT 1065 Texas Microsystems 1066 PicoPower Technology 0000 PT80C826 0001 PT86C52x [Vesuvius] 0002 PT80C524 [Nile] 8002 PT80C524 [Nile] 1067 Mitsubishi Electronics 1068 Diversified Technology 1069 Mylex Corporation 0001 DAC960P 106a Aten Research Inc 106b Apple Computer Inc. 0001 Bandit PowerPC host bridge 0002 Grand Central I/O 0003 Control Video 0004 PlanB Video-In 0007 O'Hare I/O 000e Hydra Mac I/O 0010 Heathrow Mac I/O 0017 Paddington Mac I/O 106c Hyundai Electronics America 106d Sequent Computer Systems 106e DFI, Inc 106f City Gate Development Ltd 1070 Daewoo Telecom Ltd 1071 Mitac 1072 GIT Co Ltd 1073 Yamaha Corporation 0002 YGV615 [RPA3 3D-Graphics Controller] 0003 YMF-740 0004 YMF-724 000D YMF-724F 1074 NexGen Microsystems 4e78 82c501 1075 Advanced Integrations Research 1076 Chaintech Computer Co. Ltd 1077 Q Logic 1020 ISP1020 1022 ISP1022 2100 ISP2100 1078 Cyrix Corporation 0000 5510 [Grappa] 0001 PCI_Master 0002 5520 [Cognac] 0100 5530_Legacy [Kahlua] 0101 5530_SMI [Kahlua] 0102 5530_IDE [Kahlua] 0103 5530_Audio [Kahlua] 0104 5530_Video [Kahlua] 1079 I-Bus 107a NetWorth 107b Gateway 2000 107c Goldstar 107d LeadTek Research Inc. 0000 P86C850 107e Interphase Corporation 107f Data Technology Corporation 0802 SL82C105 1080 Contaq Microsystems 0600 82C599 c693 82c693 1081 Supermac Technology 1082 EFA Corporation of America 1083 Forex Computer Corporation 0001 FR710 1084 Parador 1085 Tulip Computers Int.B.V. 1086 J. Bond Computer Systems 1087 Cache Computer 1088 Microcomputer Systems (M) Son 1089 Data General Corporation 108a Bit3 Computer Corp. 108c Oakleigh Systems Inc. 108d Olicom 0001 OC-3136/3137 0011 OC-2315 0012 OC-2325 0013 OC-2183/2185 0014 OC-2326 0021 OC-6151/6152 [RapidFire ATM PCI 155] 108e Sun Microsystems Computer Corp. 1000 EBUS 1001 Happy Meal 5000 Advanced PCI Bridge 8000 PCI Bus Module a000 Ultra IIi PCI 108f Systemsoft 1090 Encore Computer Corporation 1091 Intergraph Corporation 1092 Diamond Multimedia Systems 1093 National Instruments c801 PCI_GPIB 1094 First International Computers 1095 CMD Technology Inc 0640 PCI0640 0643 PCI0643 0646 PCI0646 0650 PBC0650A 0647 647 0670 670 1096 Alacron 1097 Appian Technology 1098 Quantum Designs (H.K.) Ltd 0001 QD-8500 0002 QD-8580 1099 Samsung Electronics Co., Ltd 109a Packard Bell 109b Gemlight Computer Ltd. 109c Megachips Corporation 109d Zida Technologies Ltd. 109e Brooktree Corporation 0350 Bt848 0351 Bt849A 036e Bt878 036f Bt879 0878 Bt878 8472 Bt8472 8474 Bt8474 109f Trigem Computer Inc. 10a0 Meidensha Corporation 10a1 Juko Electronics Ind. Co. Ltd 10a2 Quantum Corporation 10a3 Everex Systems Inc 10a4 Globe Manufacturing Sales 10a5 Racal Interlan 10a6 Informtech Industrial Ltd. 10a7 Benchmarq Microelectronics 10a8 Sierra Semiconductor 0000 STB Horizon 64 10a9 Silicon Graphics 10aa ACC Microelectronics 0000 ACCM 2188 10ab Digicom 10ac Honeywell IAC 10ad Symphony Labs 0001 W83769F 0103 SL82c103 0105 SL82c105 0565 W83C553 10ae Cornerstone Technology 10af Micro Computer Systems Inc 10b0 CardExpert Technology 10b1 Cabletron Systems Inc 10b2 Raytheon Company 10b3 Databook Inc 3106 DB87144 b106 DB87144 10b4 STB Systems Inc 10b5 PLX Technology, Inc. 9036 9036 9050 PCI <-> IOBus Bridge 9060 9060 906d 9060SD 906e 9060ES 9080 9080 10b6 Madge Networks 0001 Smart 0002 Smart 16/4 BM Mk2 PCI Ringnode 1001 Collage 155 Server 10b7 3Com Corporation 0001 3c985 1000BaseSX 3390 Token Link Velocity 5900 3c590 10BaseT [Vortex] 5950 3c595 100BaseTX [Vortex] 5951 3c595 100BaseT4 [Vortex] 5952 3c595 100Base-MII [Vortex] 9000 3c900 10BaseT [Boomerang] 9001 3c900 Combo [Boomerang] 9050 3c905 100BaseTX [Boomerang] 9051 3c905 100BaseT4 9055 3c905B 100BaseTX [Cyclone] 10b8 Standard Microsystems 0005 9432 TX 1000 37c665 1001 37C922 10b9 Acer Laboratories Inc. 1435 M1435 1445 M1445 1449 M1449 1451 M1451 1461 M1461 1489 M1489 1511 M1511 1513 M1513 1521 M1521 1523 M1523 1531 M1531 1533 M1533 1541 M1541 1543 M1543 1621 M1621 3141 M3141 3143 M3143 3145 M3145 3147 M3147 3149 M3149 3151 M3151 3307 M3307 5215 M4803 5217 M5217H 5219 M5219 5229 M5229 5235 M5225 5237 M5237 5243 M5243 5247 M5247 7101 M7101 10ba Mitsubishi Electric Corp. 10bb Dapha Electronics Corporation 10bc Advanced Logic Research 10bd Surecom Technology 0e34 NE-34PCI LAN 10be Tseng Labs International Co. 10bf Most Inc 10c0 Boca Research Inc. 10c1 ICM Co., Ltd. 10c2 Auspex Systems Inc. 10c3 Samsung Semiconductors, Inc. 10c4 Award Software International Inc. 10c5 Xerox Corporation 10c6 Rambus Inc. 10c7 Media Vision 10c8 Neomagic Corporation 0001 NM2070 [MagicGraph NM2070] 0002 NM2090 [MagicGraph 128V] 0003 NM2093 [MagicGraph 128ZV] 0004 NM2160 [MagicGraph 128XD] 0005 [MagicGraph 256AV] 0083 [MagicGraph 128ZV Plus] 10c9 Dataexpert Corporation 10ca Fujitsu Microelectr., Inc. 10cb Omron Corporation 10cc Mentor ARC Inc 10cd Advanced System Products, Inc 1200 ASC1200 [(abp940) Fast SCSI-II] 1300 ABP940-U 2300 ABP940-UW 10ce Radius 10cf Citicorp TTI 2001 mb86605 10d0 Fujitsu Limited 10d1 FuturePlus Systems Corp. 10d2 Molex Incorporated 10d3 Jabil Circuit Inc 10d4 Hualon Microelectronics 10d5 Autologic Inc. 10d6 Cetia 10d7 BCM Advanced Research 10d8 Advanced Peripherals Labs 10d9 Macronix, Inc. 0512 MX98713 0531 MX987x5 10da Compaq IPG-Austin 10db Rohm LSI Systems, Inc. 10dc CERN/ECP/EDU 0001 STAR/RD24 SCI-PCI (PMC) 0002 TAR/RD24 SCI-PCI (PMC) [ATT 2C15-3 (FPGA) SCI bridge on PCI 5 Volt card] 0021 HIPPI destination 0022 HIPPI source 10dd Evans & Sutherland 10de Nvidia Corporation 0008 NV1 0009 DAC64 0020 Riva TNT 10df Emulex Corporation 10e0 Integrated Micro Solutions Inc. 5026 IMS5026/27/28 8849 8849 9128 IMS9129 10e1 Tekram Technology Co.,Ltd. 690c 690c dc29 DC290 10e2 Aptix Corporation 10e3 Tundra Semiconductor Corp. 0000 CA91C042 [Universe] 0860 CA91C860 [QSpan] 10e4 Tandem Computers 10e5 Micro Industries Corporation 10e6 Gainbery Computer Products Inc. 10e7 Vadem 10e8 Applied Micro Circuits Corporation 5920 S5920 8043 LANai4.x [Myrinet LANai interface chip] 8062 S5933_PARASTATION 807d S5933 [Matchmaker] 809c S5933_HEPC3 10e9 Alps Electric Co., Ltd. 10ea Intergraphics Systems 1680 IGA-1680 1682 IGA-1682 10eb Artists Graphics 0101 3GA 10ec Realtek Semiconductor Co., Ltd. 8029 8029 8129 8129 8139 8139 10ed Ascii Corporation 7310 V7310 10ee Xilinx, Inc. 10ef Racore Computer Products, Inc. 10f0 Peritek Corporation 10f1 Tyan Computer 10f2 Achme Computer, Inc. 10f3 Alaris, Inc. 10f4 S-MOS Systems, Inc. 10f5 NKK Corporation a001 NDR4000 [NR4600 Bridge] 10f6 Creative Electronic Systems SA 10f7 Matsushita Electric Industrial Co., Ltd. 10f8 Altos India Ltd 10f9 PC Direct 10fa Truevision 000c TARGA 1000 10fb Thesys Gesellschaft für Mikroelektronik mbH 10fc I-O Data Device, Inc. 10fd Soyo Computer, Inc 10fe Fast Multimedia AG 10ff NCube 1100 Jazz Multimedia 1101 Initio Corporation 9100 320 P 9500 360P 1102 Creative Labs 0002 SB Live! 7002 SB Live! Daughterboard 1103 Triones Technologies, Inc. 0003 HPT343 1104 RasterOps Corp. 1105 Sigma Designs, Inc. 1106 VIA Technologies, Inc. 0505 VT 82C505 0561 VT 82C561 0571 VT82C586 IDE [Apollo] 0576 VT 82C576 3V [Apollo Master] 0585 VT82C585VP [Apollo VP1/VPX] 0586 VT82C586 ISA [Apollo VP] 0595 VT82C595 [Apollo VP2] 0596 VT82C596 ISA [Apollo PRO] 0597 VT82C597 [Apollo VP3] 0598 VT82C598 [Apollo MVP3] 0691 VT82C691 [Apollo PRO] 0926 VT82C926 [Amazon] 1000 82C570MV 1106 82C570MV 1571 VT82C416MV 1595 VT82C595/97 [Apollo VP2/97] 3038 VT82C586B USB 3040 VT82C586B ACPI 5030 VT82C596 ACPI [Apollo PRO] 6100 VT85C100A [Rhine II] 8596 VT82C596 [Apollo PRO AGP] 8597 VT82C597 [Apollo VP3 AGP] 8598 VT82C598 [Apollo MVP3 AGP] 1107 Stratus Computers 1108 Proteon, Inc. 0100 p1690plus_AA 0101 p1690plus_AB 1109 Cogent Data Technologies, Inc. 1400 EM110TX [EX110TX PCI Fast Ethernet Adapter] 110a Siemens Nixdorf AG 6120 SZB6120 110b Chromatic Research Inc. 110c Mini-Max Technology, Inc. 110d Znyx Advanced Systems 110e CPU Technology 110f Ross Technology 1110 Powerhouse Systems 1111 Santa Cruz Operation 1112 RNS - Div. of Meret Communications Inc 1113 Accton Technology Corporation 1211 SMC2-1211TX 1114 Atmel Corporation 1115 3D Labs 1116 Data Translation 1117 Datacube, Inc 1118 Berg Electronics 1119 ICP Vortex Computersysteme GmbH 0000 GDT6000/6020/6050 0001 GDT6000b/6010 0002 GDT6110/6510 0003 GDT6120/6520 0004 GDT6530 0005 GDT6550 0006 GDT6x17 0007 GDT6x27 0008 GDT6537 0009 GDT5557 000a GDT6x15 000b GDT6x25 000c GDT6535 000d GDT6555 0100 GDT 6117RP/6517RP 0101 GDT 6127RP/6527RP 0102 GDT 6537RP 0103 GDT 6557RP 0104 GDT 6111RP/6511RP 0105 GDT 6121RP/6521RP 0110 GDT 6117RP1/6517RP1 0111 GDT 6127RP1/6527RP1 0112 GDT 6537RP1 0113 GDT 6557RP1 0114 GDT 6111RP1/6511RP1 0115 GDT 6121RP1/6521RP1 0118 GDT 6x18RD 0119 GDT 6x28RD 011A GDT 6x38RD 011B GDT 6x58RD 0120 GDT 6117RP2/6517RP2 0121 GDT 6127RP2/6527RP2 0122 GDT 6537RP2 0123 GDT 6557RP2 0124 GDT 6111RP2/6511RP2 0125 GDT 6121RP2/6521RP2 0168 GDT 7x18RN 0169 GDT 7x28RN 016A GDT 7x38RN 016B GDT 7x58RN 0210 GDT 6x19RD 0211 GDT 6x29RD 0260 GDT 7x19RN 0261 GDT 7x29RN 111a Efficient Networks, Inc 0000 155P-MF1 (FPGA) 0002 155P-MF1 (ASIC) 111b Teledyne Electronic Systems 111c Tricord Systems Inc. 111d Integrated Device Tech 111e Eldec 111f Precision Digital Images 1120 EMC Corporation 1121 Zilog 1122 Multi-tech Systems, Inc. 1123 Excellent Design, Inc. 1124 Leutron Vision AG 1125 Eurocore 1127 FORE Systems Inc 0210 PCA-200PC 0300 PCA-200E 1129 Firmworks 112a Hermes Electronics Company, Ltd. 112b Linotype - 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Does anyone know the correct ID? # 0701 Lucent DSP1645 [Mars] 117b L G Electronics, Inc. 117c Atto Technology 117d Becton & Dickinson 117e T/R Systems 117f Integrated Circuit Systems 1180 Ricoh Co Ltd 0465 RL5C465 0466 RL5C466 0475 RL5C475 0478 RL5C478 1181 Telmatics International 1183 Fujikura Ltd 1184 Forks Inc 1185 Dataworld International Ltd 1186 D-Link System Inc 1187 Advanced Technology Laboratories, Inc. 1188 Shima Seiki Manufacturing Ltd. 1189 Matsushita Electronics Co Ltd 118a Hilevel Technology 118b Hypertec Pty Limited 118c Corollary, Inc 0014 PCIB [C-bus II to PCI bus host bridge chip] 118d BitFlow Inc 0001 n/a [Raptor-PCI framegrabber] 118e Hermstedt GmbH 118f Green Logic 1191 Artop Electronic Corp 0004 ATP8400 0005 ATP850UF 1192 Densan Company Ltd 1193 Zeitnet Inc. 0001 1221 0002 1225 1194 Toucan Technology 1195 Ratoc System Inc 1196 Hytec Electronics Ltd 1197 Gage Applied Sciences, Inc. 1198 Lambda Systems Inc 1199 Attachmate Corporation 119a Mind Share, Inc. 119b Omega Micro Inc. 1221 82C092G 119c Information Technology Inst. 119d Bug, Inc. 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Inc 11a6 Pure Data Ltd. 11a7 Power Computing Corp. 11a8 Systech Corp. 11a9 InnoSys Inc. 11aa Actel 11ab Galileo Technology Ltd. 0146 GT-64010 4801 GT-48001 11ac Canon Information Systems Research Aust. 11ad Lite-On Communications Inc 0002 LNE100TX 11ae Aztech System Ltd 11af Avid Technology Inc. 11b0 V3 Semiconductor Inc. 0292 V292PBC [Am29030/40 Bridge] 0960 V96xPBC c960 V96DPC 11b1 Apricot Computers 11b2 Eastman Kodak 11b3 Barr Systems Inc. 11b4 Leitch Technology International 11b5 Radstone Technology Plc 11b6 United Video Corp 11b8 XPoint Technologies, Inc 11b9 Pathlight Technology Inc. 11ba Videotron Corp 11bb Pyramid Technology 11bc Network Peripherals Inc 0001 NP-PCI 11bd Pinnacle Systems Inc. 11be International Microcircuits Inc 11bf Astrodesign, Inc. 11c0 Hewlett Packard 11c1 Lucent Microelectronics 0440 Modem L56xMF 0441 Unknown 56K Modem [Mars?] 0442 Unknown 56K Modem 044a Modem F-1156IV [V90 56KFlex] 0480 Modem with Venus chipset [V90 56KFlex] 11c2 Sand Microelectronics 11c4 Document Technologies, Inc 11c5 Shiva Corporation 11c6 Dainippon Screen Mfg. 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Ltd 1379 Asahi Kasei Microsystems Co Ltd 137a Mark of the Unicorn Inc 137b PPT Vision 137c Iwatsu Electric Co Ltd 137d Dynachip Corporation 137e Patriot Scientific Corporation 137f Japan Satellite Systems Inc 1380 Sanritz Automation Co Ltd 1381 Brains Co. Ltd 1382 Marian - Electronic & Software 1383 Controlnet Inc 1384 Reality Simulation Systems Inc 1385 Netgear 620a GA620 1386 Video Domain Technologies 1387 Systran Corp 1388 Hitachi Information Technology Co Ltd 1389 Applicom International 0001 PCI1500PFB [Intelligent fieldbus adaptor] 138a Fusion Micromedia Corp 138b Tokimec Inc 138c Silicon Reality 138d Future Techno Designs pte Ltd 138e Basler GmbH 138f Patapsco Designs Inc 1390 Concept Development Inc 1391 Development Concepts Inc 1392 Medialight Inc 1393 Moxa Technologies Co Ltd 1394 Level One Communications 1395 Ambicom Inc 1396 Cipher Systems Inc 1397 Cologne Chip Designs GmbH 1398 Clarion co. Ltd 1399 Rios systems Co Ltd 139a Alacritech Inc 139b Mediasonic Multimedia Systems Ltd 139c Quantum 3d Inc 139d EPL limited 139e Media4 139f Aethra s.r.l. 13a0 Crystal Group Inc 13a1 Kawasaki Heavy Industries Ltd 13a2 Ositech Communications Inc 13a3 Hi-Fn 13a4 Rascom Inc 13a5 Audio Digital Imaging Inc 13a6 Videonics Inc 13a7 Teles AG 13a8 Exar Corp. 13a9 Siemens Medical Systems, Ultrasound Group 13aa Broadband Networks Inc 13ab Arcom Control Systems Ltd 13ac Motion Media Technology Ltd 13ad Nexus Inc 13ae ALD Technology Ltd 13af T.Sqware 13b0 Maxspeed Corp 13b1 Tamura corporation 13b2 Techno Chips Co. Ltd 13b3 Lanart Corporation 13b4 Wellbean Co Inc 13b5 ARM 13b6 Dlog GmbH 13b7 Logic Devices Inc 13b8 Nokia Telecommunications oy 13b9 Elecom Co Ltd 13ba Oxford Instruments 13bb Sanyo Technosound Co Ltd 13bc Bitran Corporation 13bd Sharp corporation 13be Miroku Jyoho Service Co. Ltd 13bf Sharewave Inc 13c0 Microgate Corporation 13c1 3ware Inc 13c2 Technotrend Systemtechnik GmbH 13c3 Janz Computer AG 13c4 Phase Metrics 13c5 Alphi Technology Corp 13c6 Condor Engineering Inc 13c7 Blue Chip Technology Ltd 13c8 Apptech Inc 13c9 Eaton Corporation 13ca Iomega Corporation 13cb Yano Electric Co Ltd 13cc Metheus Corporation 13cd Compatible Systems Corporation 13ce Cocom A/S 13cf Studio Audio & Video Ltd 13d0 Techsan Electronics Co Ltd 13d1 Abocom Systems Inc 13d2 Shark Multimedia Inc 13d3 IMC Networks 13d4 Graphics Microsystems Inc 13d5 Media 100 Inc 13d6 K.I. Technology Co Ltd 13d7 Toshiba Engineering Corporation 13d8 Phobos corporation 13d9 Apex PC Solutions Inc 13da Intresource Systems pte Ltd 13db Janich & Klass Computertechnik GmbH 13dc Netboost Corporation 13dd Multimedia Bundle Inc 13de ABB Robotics Products AB 13df E-Tech Inc 13e0 GVC Corporation 13e1 Silicom Multimedia Systems Inc 13e2 Dynamics Research Corporation 13e3 Nest Inc 13e4 Calculex Inc 13e5 Telesoft Design Ltd 13e6 Argosy research Inc 13e7 NAC Incorporated 13e8 Chip Express Corporation 13e9 Chip Express Corporation 13ea Dallas Semiconductor 13eb Hauppauge Computer Works Inc 13ec Zydacron Inc 13ed Raytheion E-Systems 13ee Hayes Microcomputer Products Inc 13ef Coppercom Inc 13f0 Sundance technology Inc 13f1 Oce' - Technologies B.V. 13f2 Ford Microelectronics Inc 13f3 Mcdata Corporation 13f4 Troika Design Inc 13f5 Kansai Electric Co. Ltd 13f6 C-Media Electronics Inc 0100 CMI8338 13f7 Wildfire Communications 13f8 Ad Lib Multimedia Inc 13f9 NTT Advanced Technology Corp. 13fa Pentland Systems Ltd 13fb Aydin Corp 13fc Computer Peripherals International 13fd Micro Science Inc 13fe Advantech Co. Ltd 13ff Silicon Spice Inc 1400 Artx Inc 1401 CR-Systems A/S 1402 Meilhaus Electronic GmbH 1403 Ascor Inc 1404 Fundamental Software Inc 1405 Excalibur Systems Inc 1406 Oce' Printing Systems GmbH 1407 Lava Computer mfg Inc 1408 Aloka Co. Ltd 1409 Timedia Technology Co Ltd 140a DSP Research Inc 140b Ramix Inc 140c Elmic Systems Inc 140d Matsushita Electric Works Ltd 140e Goepel Electronic GmbH 140f Salient Systems Corp 1410 Midas lab Inc 1411 Ikos Systems Inc 1412 IC Ensemble Inc 1413 Addonics 1414 Microsoft Corporation 1415 Oxford Semiconductor Ltd 1416 Multiwave Innovation pte Ltd 1417 Convergenet Technologies Inc 1418 Kyushu electronics systems Inc 1419 Excel Switching Corp 141a Apache Micro Peripherals Inc 141b Zoom Telephonics Inc 141d Digitan Systems Inc 141e Fanuc Ltd 141f Visiontech Ltd 1420 Psion Dacom plc 1421 Ads Technologies Inc 1422 Ygrec Systems Co Ltd 1423 Custom Technology Corp. 1424 Videoserver Connections 1425 ASIC Designers Inc 1426 Storage Technology Corp. 1427 Better On-Line Solutions 1428 Edec Co Ltd 1429 Unex Technology Corp. 142a Kingmax Technology Inc 142b Radiolan 142c Minton Optic Industry Co Ltd 142d Pix stream Inc 142e Vitec Multimedia 142f Radicom Research Inc 1430 ITT Aerospace/Communications Division 1431 Gilat Satellite Networks 1432 Edimax Computer Co. 1433 Eltec Elektronik GmbH 1435 Real Time Devices US Inc. 1436 CIS Technology Inc 14b9 Aironet 0001 PC4800 1668 Action Tec Electronics Inc 1b13 Jaton Corp 1c1c Symphony 0001 82C101 1de1 Tekram Technology Co.,Ltd. 690c 690c dc29 DC290 21c3 21st Century Computer Corp. 270b Xantel Corporation 270f Chaintech Computer Co. Ltd 3388 Hint Corp 3d3d 3DLabs 0001 GLINT 300SX 0002 GLINT 500TX 0003 GLINT Delta 0004 Permedia 0006 GLINT MX 4005 Avance Logic Inc. 2064 ALG2064i 2301 ALG2301 2302 ALG2302 4444 Internext Compression Inc 4680 Umax Computer Corp 4843 Hercules Computer Technology Inc 4978 Axil Computer Inc 4a14 NetVin 5000 PCI NV5000SC 4ddc ILC Data Device Corp 5053 Voyetra Technologies 5143 Qualcomm Inc 5333 S3 Inc. 0551 Plato/PX (system) 5631 86C325 [ViRGE] 8810 86C764_0 [Trio 32 vers 0] 8811 86C764_1 [Trio 32/64 vers 1] 8812 Aurora64V+ 8813 86C764_3 [Trio 32/64 vers 3] 8814 Trio64UV+ 8815 Aurora128 883d ViRGE/VX 8880 Vision 868 vers 0 8881 Vision 868 vers 1 8882 Vision 868 vers 2 8883 Vision 868 vers 3 88b0 Vision 928 vers 0 88b1 Vision 928 vers 1 88b2 Vision 928 vers 2 88b3 Vision 928 vers 3 88c0 Vision 864 vers 0 88c1 Vision 864 vers 1 88c2 86C864 88c3 86C864 88d0 Vision 964 vers 0 88d1 Vision 964 vers 1 88d2 86C964 88d3 86C964 88f0 Vision 968 88f1 86C968 88f2 86C968 88f3 86C968 8901 Trio64V2/DX or /GX 8902 Plato/PX (graphics) 8a01 ViRGE/DX or /GX 8a10 ViRGE/GX2 8c01 ViRGE/MX 8c02 ViRGE/MX+ 8c03 ViRGE/MX+MV ca00 SonicVibes 5555 Genroco, Inc 0003 TURBOstor HFP-832 [HiPPI NIC] 6374 c't Magazin für Computertechnik 6773 GPPCI 6666 Decision Computer International Co. 0001 PCCOM4 8008 Quancm Electronic GmbH 0010 WDOG1 [PCI-Watchdog 1] 0011 PWDOG2 [Watchdog2/PCI] 8086 Intel Corporation 0039 21145 0482 82375EB 0483 82424ZX [Saturn] 0484 82378IB [SIO ISA Bridge] 0486 82430ZX [Aries] 04a3 82434LX [Mercury/Neptune] 0960 80960RP [i960 RP Microprocessor/Bridge] 1221 82092AA_0 1222 82092AA_1 1223 SAA7116 1226 82596 1227 82865 1228 82556 1229 82557 122d 430FX - 82437FX TSC [Triton I] 122e 82371FB PIIX ISA [Triton I] 1230 82371FB PIIX IDE [Triton I] 1234 430MX - 82371MX MPIIX [430MX PCIset - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)] 1235 430MX - 82437MX MTSC [430MX PCIset - 82437MX Mobile System Controller (MTSC) and 82438MX Mobile Data Path (MTDP)] 1237 440FX - 82441FX PMC [Natoma] 124b 82380FB 1250 430HX - 82439HX TXC [Triton II] 1960 80960RP [i960RP Microprocessor] 7000 82371SB PIIX3 ISA [Natoma/Triton II] 7010 82371SB PIIX3 IDE [Natoma/Triton II] 7020 82371SB PIIX3 USB [Natoma/Triton II] 7030 430VX - 82437VX TVX [Triton VX] 7100 430TX - 82439TX MTXC 7110 82371AB PIIX4 ISA 7111 82371AB PIIX4 IDE 7112 82371AB PIIX4 USB 7113 82371AB PIIX4 ACPI 7180 440LX - 82443LX Host bridge 7181 440LX - 82443LX AGP bridge 7190 440BX/ZX - 82443BX/ZX Host bridge 7191 440BX/ZX - 82443BX/ZX AGP bridge 7192 440BX/ZX - 82443BX/ZX Host bridge (AGP disabled) 71a0 440GX - 82443GX Host bridge 71a1 440GX - 82443GX AGP bridge 71a2 440GX - 82443GX Host bridge (AGP disabled) 7800 i740 84c4 450KX/GX [Orion] - 82454KX/GX PCI bridge 84c5 450KX/GX [Orion] - 82453KX/GX Memory controller 84ca 450NX - 82451NX Memory & I/O Controller 84cb 450NX - 82454NX PCI Expander Bridge 8800 Trigem Computer Inc. 8888 Silicon Magic 8e0e Computone Corporation 8e2e KTI 3000 ET32P2 9004 Adaptec 1078 AIC-7810 2178 AIC-7821 5078 AIC-7850 5178 7851 5278 7852 5575 2930 5578 AIC-7855 5800 AIC-5800 6038 AIC-3860 # FIXME: This is a cardbus card. The declaration may be duplicative. 6075 AIC-1480 6078 AIC-7860 6178 AIC-7861 6278 AIC-7860 6378 AIC-7860 7078 AIC-7870 7178 AIC-7871 7278 AIC-7872 7378 AIC-7873 7478 AIC-7874 [AHA-2944] 7578 7875 7678 7876 7895 AIC-7895 8078 AIC-7880U 8178 AIC-7881U 8278 AIC-7882U 8378 AIC-7883U 8478 AIC-7884U 8578 7885 8678 7886 8778 7887 8878 7888 8b78 ABA-1030 9005 Adaptec 0010 2940U2 0011 2930U2 0013 78902 001f 7890 0050 3940U2 0051 3950U2D 005f 7896 0080 7892A 0081 7892B 0083 7892D 008f 7892P 00c0 7899A 00c1 7899B 00c3 7899D 00cf 7899P 907f Atronics 2015 IDE-2015PL 9412 Holtek 6565 6565 a200 NEC Corporation a259 Hewlett Packard a25b Hewlett Packard GmbH PL24-MKT a304 Sony a727 3Com Corporation aa42 Scitex Digital Video b1b3 Shiva Europe Limited c001 TSI Telsys c0a9 Micron/Crucial Technology c0de Motorola c0fe Motion Engineering, Inc. cafe Chrysalis-ITS d4d4 Dy4 Systems Inc e159 Tiger Jet Network Inc. 0001 300 ecc0 Echo Corporation edd8 ARK Logic Inc a091 1000PV [Stingray] a099 2000PV [Stingray] a0a1 2000MT a0a9 2000MI # List of known device classes and subclasses C 00 Unclassified device 0000 Non-VGA unclassified device 0001 VGA compatible unclassified device C 01 Mass storage controller 0000 SCSI storage controller 0001 IDE interface 0002 Floppy disk controller 0003 IPI bus controller 0004 RAID bus controller 0080 Unknown mass storage controller C 02 Network controller 0000 Ethernet controller 0001 Token ring network controller 0002 FDDI network controller 0003 ATM network controller 0080 Network controller C 03 Display controller 0000 VGA compatible controller 0001 XGA compatible controller 0080 Display controller C 04 Multimedia controller 0000 Multimedia video controller 0001 Multimedia audio controller 0080 Multimedia controller C 05 Memory controller 0000 RAM memory 0001 FLASH memory 0080 Memory C 06 Bridge 0000 Host bridge 0001 ISA bridge 0002 EISA bridge 0003 MicroChannel bridge 0004 PCI bridge 0005 PCMCIA bridge 0006 NuBus bridge 0007 CardBus bridge 0080 Bridge C 07 Communication controller 0000 Serial controller 0001 Parallel controller 0080 Communication controller C 08 Generic system peripheral 0000 PIC 0001 DMA controller 0002 Timer 0003 RTC 0080 System peripheral C 09 Input device controller 0000 Keyboard controller 0001 Digitizer Pen 0002 Mouse controller 0080 Input device controller C 0A Docking station 0000 Generic Docking Station 0080 Docking Station C 0B Processor 0000 386 0001 486 0002 Pentium 0010 Alpha 0020 Power PC 0040 Co-processor C 0C Serial bus controller 0000 FireWire (IEEE 1394) 0001 ACCESS Bus 0002 SSA 0003 USB Controller 0004 Fiber Channel C 0E Intelligent controller 0000 I2O S 10b4 STB Systems Inc 273e Velocity 4400 ltmodem-0.0.5/pciutils.h100644 1750 144 2625 6652164560 12700 0ustar users/* * $Id: pciutils.h,v 1.12 1999/01/22 21:04:59 mj Exp $ * * Linux PCI Utilities -- Declarations * * Copyright (c) 1997--1999 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "lib/pci.h" #define PCIUTILS_VERSION PCILIB_VERSION void __attribute__((noreturn)) die(char *msg, ...); void *xmalloc(unsigned int howmuch); int parse_generic_option(int i, struct pci_access *pacc, char *optarg); #ifdef HAVE_PM_LINUX_PROC #define GENOPT_PROC "P:" #define GENHELP_PROC "-P \tUse specified directory instead of " PATH_PROC_BUS_PCI "\n" #else #define GENOPT_PROC #define GENHELP_PROC #endif #ifdef HAVE_PM_INTEL_CONF #define GENOPT_INTEL "H:" #define GENHELP_INTEL "-H \tUse direct hardware access ( = 1 or 2)\n" #else #define GENOPT_INTEL #define GENHELP_INTEL #endif #ifdef HAVE_PM_SYSCALLS #define GENOPT_SYSCALLS "S" #define GENHELP_SYSCALLS "-S\t\tUse direct hardware access via syscalls\n" #else #define GENOPT_SYSCALLS #define GENHELP_SYSCALLS #endif #ifdef HAVE_PM_DUMP #define GENOPT_DUMP "F:" #define GENHELP_DUMP "-F \tRead configuration data from given file\n" #else #define GENOPT_DUMP #define GENHELP_DUMP #endif #define GENERIC_OPTIONS "G" GENOPT_PROC GENOPT_INTEL GENOPT_SYSCALLS GENOPT_DUMP #define GENERIC_HELP GENHELP_PROC GENHELP_INTEL GENHELP_SYSCALLS GENHELP_DUMP \ "-G\t\tEnable PCI access debugging\n" ltmodem-0.0.5/ltmodem.h100444 0 0 7713 6755677300 13073 0ustar rootroot/* * $Id: ltmodem.h,v 1.4 1999/08/16 03:00:16 root Exp $ * * Lucent PCI modem diagnostics tool. * * Copyright (c) 1999 Richard J.M. Close * * Can be freely distributed and used under the terms of the GNU GPL. */ #include #include #include #include #include #include #include "portIO.h" #include "irq.h" /* Format strings used for IRQ numbers and memory addresses */ #ifdef ARCH_SPARC64 #define IRQ_FORMAT "%08x" #else #define IRQ_FORMAT "%d" #endif #ifdef HAVE_64BIT_ADDRESS #define ADDR_FORMAT "%016Lx" #else #define ADDR_FORMAT "%08lx" #endif #ifdef ARCH_SPARC64 #define IO_FORMAT "%016Lx" #elif defined(HAVE_64BIT_ADDRESS) #define IO_FORMAT "%04Lx" #else #define IO_FORMAT "%04lx" #endif #define LTMODEM_VERSION "0.0.5" struct device { struct device *next; struct pci_dev *dev; unsigned int config_cnt; byte config[256]; }; /* Communication with libpci */ static struct pci_access *pacc; /* Our view of the PCI bus */ static struct device *first_dev; static struct device *modem_dev; /* Tree output */ struct bridge { struct bridge *chain; /* Single-linked list of bridges */ struct bridge *next, *child; /* Tree of bridges */ struct bus *first_bus; /* List of busses connected to this bridge */ unsigned int primary, secondary, subordinate; /* Bus numbers */ struct device *br_dev; }; struct bus { unsigned int number; struct bus *sibling; struct device *first_dev, **last_dev; }; /* Options */ static int modem; /* Boolean: modem has been found = 1 */ /*static int verbose; Show detailed information */ static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */ static struct pci_filter filter; /* Device filter */ /* general scanning stuff. */ static struct device * scan_device(struct pci_dev *p); static void scan_devices(void); static int check_root(void); static int config_fetch(struct device *d, unsigned int pos, unsigned int len); /* Config space accesses */ static inline byte get_conf_byte(struct device *d, unsigned int pos); static word get_conf_word(struct device *d, unsigned int pos); static u32 get_conf_long(struct device *d, unsigned int pos); /* Count used to access bases of htype0 devices. */ static int htype0_cnt = 6; /* Array to hold IO addresses and their width (in bytes). */ unsigned int io_address[6]; unsigned int io_length[6]; /* The number of I/O ports found, = length of io_address. */ static unsigned int io_cnt; /* Sorting */ static int compare_them(const void *A, const void *B); static void sort_them(void); /* Normal output */ #define FLAG(x,y) ((x & y) ? '+' : '-') static void show_bases(struct device *d, int cnt); static void show_htype0(struct device *d); static struct bus * find_bus(struct bridge *b, unsigned int n); static struct bus * new_bus(struct bridge *b, unsigned int n); static void insert_dev(struct device *d, struct bridge *b); /* Bus mapping mode */ struct bus_bridge { struct bus_bridge *next; byte this, dev, func, first, last, bug; }; struct bus_info { byte exists; byte guestbook; struct bus_bridge *bridges, *via; }; static struct bus_info *bus_info; static void do_map_bridges(int bus, int min, int max); /* Show hexadecimal dump of first 64 bytes of the PCI configuration space (the standard header). */ static void show_hex_dump(struct device *d); /* Lucent modem specific stuff. */ static int find_modem(void); static void show_modem(void); /* Modem monitoring functions. */ static void monitor_modem(void); static int set_monitoring_interval(void); static void continous_monitoring(int monitor_type, int monitoring_interval); static void redisplay_modem_regs(void); /* Modem writing functions. */ static void set_modem(void); /* Interactively set the control register. */ static void set_modem_cont_reg(void); /* Interactively write to the IO ports. */ static void set_modem_io(void); /* Main command menu. */ void main_menu(void); void setup_irq(void); void io_init(void); ltmodem-0.0.5/ltmodem.c,v100444 0 0 64665 6755677211 13362 0ustar rootroothead 1.4; access; symbols; locks; strict; comment @ * @; 1.4 date 99.08.16.02.59.21; author root; state Exp; branches; next 1.3; 1.3 date 99.07.21.03.30.34; author root; state Exp; branches; next 1.2; 1.2 date 99.07.05.04.04.46; author root; state Exp; branches; next 1.1; 1.1 date 99.07.05.03.51.18; author root; state Exp; branches; next ; desc @@ 1.4 log @Included Pavel's updates and tidy ups. @ text @/* * $Id: ltmodem.c,v 1.3 1999/07/21 03:30:34 root Exp root $ * * Lucent PCI modem diagnostics tool. * * Copyright (c) 1999 Richard J.M. Close * Copyright (c) 1999 Pavel Machek * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "ltmodem.h" unsigned int portbase; unsigned int modem_irq; int verbose = 0; /* Main program. */ int main(int argc, char **argv) { char c; sync(); /* it's for your own protection */ setvbuf(stdout, NULL, _IONBF, 0); puts("ltmodem version " LTMODEM_VERSION); modem = 0; io_cnt = 0; pacc = pci_alloc(); pacc->error = die; pci_filter_init(pacc, &filter); pci_init(pacc); scan_devices(); sort_them(); /* If modem is found then it sets modem_dev to device structure for modem, and modem =1 */ if ( !find_modem() ) { printf ("Sorry, no Lucent PCI modem that I know of was found.\n"); printf ("If you have one fitted then please mail me with the details\n"); printf ("at: richard@@close.u-net.com please include an output from\n"); printf ("cat /proc/pci and as much info. on the card as possible.\n"); exit(1); } while ((c = getopt(argc, argv, "imovth" )) != -1) { switch(c) { case 'i': show_modem(); main_menu(); break; case 't': show_modem(); setup_irq(); io_init(); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x7e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0xff); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x00); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x25); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x89); sleep(1); dp_change_mercury_gain(0x88, 0x80, 0x6b, 0x1e); sleep(1); break; case 'o': show_modem(); setup_irq(); io_init(); //dp_offhook_cmd(); /* go_offhook(); -- seems to do something slightly different */ #if 0 while(1) { printf( "%4x %4x %4x %4x %4x %4x\n", readbio(0x1002), readbio(0x1120), readbio(0xffff), readbio(0xf0ff), readbio(0xf1ff), readbio(0xf2ff)); sleep(1); } #endif break; case 'm': continous_monitoring(3, 1000); break; case 'v': verbose++; break; case 'h': default: printf( "Usage: ltmodem [-imovt]\n" ); printf( "-i interative use.\n-m monitoring ports/registers.\n"); printf( "-o run offhook command.\n-v increase level of verbosity.\n"); printf( "-t mess around with mercury gain (whatever that is). \n"); goto exit; } } exit: pci_cleanup(pacc); return 0; } void setup_irq(void) { printf( "Removing i2sig\n" ); system("rmmod i2sig"); // Setup IRQ variable used by other stuff. modem_irq = modem_dev->dev->irq; #if 0 char buf[10240]; sprintf( buf, "insmod ./i2sig.o irq=%d pid=%d", modem_irq, getpid()); printf( "Installing new i2sig: %s\n", buf ); system(buf); #endif signal_init(); } /* Find any known any Lucent modems. */ static int find_modem(void) { struct device *d; int i; for(d=first_dev; d; d=d->next) { struct pci_dev *p = d->dev; /* Only cards with vendor ID = Lucent!. */ if (p->vendor_id == 0x11c1) { modem_dev = d; modem = 1; io_cnt = 0; /* Record I/O addresses. */ for(i=0; ibase_addr[i]; u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (flg == 0xffffffff) flg = 0; if (!pos && !flg) continue; if (flg & PCI_BASE_ADDRESS_SPACE_IO) { io_address[i] = pos & PCI_BASE_ADDRESS_IO_MASK; io_length[i] = (io_address[i] < 0x3f8) ? 8 : 256; io_cnt = i; } } } } return modem; } // Show any found modem. static void show_modem(void) { int c; struct pci_dev *p = modem_dev->dev; byte classbuf[128], devbuf[128]; unsigned int irq = p->irq; byte latency = get_conf_byte( modem_dev, PCI_LATENCY_TIMER); word status = get_conf_word( modem_dev, PCI_STATUS); word cmd = get_conf_word( modem_dev, PCI_COMMAND); byte max_lat, min_gnt; word subsys_v, subsys_d; char ssnamebuf[256]; printf("%02x:%02x.%x %s: %s", p->bus, p->dev, p->func, pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word( modem_dev, PCI_CLASS_DEVICE), 0), pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id)); if (c = get_conf_byte( modem_dev, PCI_REVISION_ID)) printf(" (rev %02x)", c); if (c = get_conf_byte( modem_dev, PCI_CLASS_PROG)) printf(" (prog-if %02x)", c); putchar('\n'); max_lat = get_conf_byte( modem_dev, PCI_MAX_LAT); min_gnt = get_conf_byte( modem_dev, PCI_MIN_GNT); subsys_v = get_conf_word( modem_dev, PCI_SUBSYSTEM_VENDOR_ID); subsys_d = get_conf_word( modem_dev, PCI_SUBSYSTEM_ID); if (subsys_v && subsys_v != 0xffff) printf("\tSubsystem: %s\n", pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, subsys_v, subsys_d)); printf("\tFlags: "); if (cmd & PCI_COMMAND_MASTER) printf("bus master, "); if (cmd & PCI_COMMAND_VGA_PALETTE) printf("VGA palette snoop, "); if (cmd & PCI_COMMAND_WAIT) printf("stepping, "); if (cmd & PCI_COMMAND_FAST_BACK) printf("fast Back2Back, "); if (status & PCI_STATUS_66MHZ) printf("66Mhz, "); if (status & PCI_STATUS_UDF) printf("user-definable features, "); printf("%s devsel", ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" : ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" : ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??"); if (cmd & PCI_COMMAND_MASTER) printf(", latency %d", latency); if (irq) printf(", IRQ " IRQ_FORMAT, irq); putchar('\n'); show_htype0( modem_dev); } // Modem monitoring functions. void monitor_modem(void) { // Value input by user. char input = 'z'; // Monitoring activity type: // registers = 1, I/O = 2. int monitor_type = 1; // Monitoring period in milliseconds, defaults to one second. int monitoring_interval = 1000; while (input != 'Q') { // Ignore the newline char. if (input != '\n') { printf ("***************************************************\n"); printf ("monitoring menu (Monitor monitorIo monitorRegs monitorBoth iNterval Quit): "); } // Get user input in uppercase. input = toupper (getchar()); switch (input) { case 'M': continous_monitoring(monitor_type, monitoring_interval); break; case 'I': printf( "Will monitor I/O ports.\n" ); monitor_type = 2; break; case 'R': printf( "Will monitor PCI registers.\n" ); monitor_type = 1; break; case 'B': printf( "Will monitor I/O ports and PCI registers.\n" ); monitor_type = 3; break; case 'N': monitoring_interval = set_monitoring_interval(); break; case '\n': break; case 'Q': break; default: printf ("Illegal option: %c\n", input); } } } int set_monitoring_interval(void){ // Value input by user. int input = 0; char trash; // Allow user to set interval. printf ("Set monitoring interval (in miliseconds): "); scanf ("%d%c", &input, &trash); if (input > 0) { // Return the user's value. printf ("Interval set to %d milliseconds.\n", input); return input; } else { // Default to one second. printf ("Illegal interval, using 1 second default.\n"); return 1000; } } void continous_monitoring(int monitor_type, int monitoring_interval){ // Iteration loop variable. unsigned int i; // Main monitoring loop. while (1) { // Monitor registers or I/O depending on current setting. if (monitor_type & 1) { // Re-scan device. pci_scan_bus(pacc); modem_dev = scan_device(modem_dev->dev); // Show the hex. show_hex_dump(modem_dev); } if (monitor_type & 2) { // Get access to all of I/O space. if (iopl(3) < 0) { perror("ltmodem: iopl()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Read the ports. printf("I/O ports\n "); // Loop for each known port. for (i=1;i<=io_cnt;i++) { unsigned int j; printf( "%x: ", io_address[i] ); for (j=0; jdev); /* Show the hex. */ show_hex_dump(modem_dev); } void set_modem_cont_reg(void) { /* value input by user. */ int input = 0; /* CR input after first char. */ char trash; /* Allow user to set control register. */ printf ("Set control register (value in hex): "); scanf ("%x%c", &input, &trash); printf ("Writing %x to control register.\n", input); /* command register is at address 04. */ pci_write_word(modem_dev->dev, 0x04, input); } void set_modem_io(void) { unsigned int i; /* value input by user. */ unsigned int input = 0; unsigned int offset = 0; /* CR input after first char. */ char trash; if (io_cnt > 0) { printf("I/O ports found:\n"); for(i=1; i<=io_cnt; i++){ printf("%d - I/O port at %x.\n", i, io_address[i]); } // Select the port. printf ("Port to write long word at (in hex): "); scanf ("%x%c", &input, &trash); // Write the value. if ((input > 0) && (input <= io_cnt)) { // Allow user to write to selected I/O port. i = input; printf ("Write to %x, enter value (in hex): ", io_address[i]); scanf ("%x%c", &input, &trash); // Get offset to use. printf ("Offset to use (in hex): "); scanf ("%x%c", &offset, &trash); printf ("Writing %2x to I/O port %x + %x.\n", input, io_address[i], offset); // Write value to port. WRITE_PORT_UCHAR ((io_address[i] + offset), input); ///* Delay 10ms. */ usleep(10000); /* Read back the port. */ printf("Read back value: %2x.\n", READ_PORT_UCHAR(io_address[i] + offset)); } } } /* Main command menu. */ void main_menu(void) { /* char input by user. */ char input = 'z'; while (input != 'Q') { // Ignore the newline char. if (input != '\n') { printf ("main menu (Monitor Write Quit): "); } // Get user input in uppercase. input = toupper (getchar()); switch (input) { case 'M': monitor_modem(); break; case 'W': set_modem(); break; case '\n': break; case 'Q': break; default: printf ("Illegal option: %c\n", input); } } /* Bye bye... */ printf ("User stopped ltmodem.\n"); } /******************************************************************************** * * PCI utilities. * *********************************************************************************/ static struct device * scan_device(struct pci_dev *p) { int how_much = 0x40; /* First 64 bytes. */ struct device *d; if (!pci_filter_match(&filter, p)) return NULL; d = xmalloc(sizeof(struct device)); bzero(d, sizeof(*d)); d->dev = p; if (!pci_read_block(p, 0, d->config, how_much)) die("Unable to read %d bytes of configuration space.", how_much); if (how_much < 128 && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS) { /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */ if (!pci_read_block(p, 0, d->config+64, 64)) die("Unable to read cardbus bridge extension data."); how_much = 128; } d->config_cnt = how_much; pci_setup_cache(p, d->config, d->config_cnt); pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE); return d; } static void scan_devices(void) { struct device *d; struct pci_dev *p; pci_scan_bus(pacc); for(p=pacc->devices; p; p=p->next) if (d = scan_device(p)) { d->next = first_dev; first_dev = d; } } static int check_root(void) { static int is_root = -1; if (is_root < 0) is_root = !geteuid(); return is_root; } static int config_fetch(struct device *d, unsigned int pos, unsigned int len) { if (pos + len < d->config_cnt) return 1; if (pacc->method != PCI_ACCESS_DUMP && !check_root()) return 0; return pci_read_block(d->dev, pos, d->config + pos, len); } /* Config space accesses */ static inline byte get_conf_byte(struct device *d, unsigned int pos) { return d->config[pos]; } static word get_conf_word(struct device *d, unsigned int pos) { return d->config[pos] | (d->config[pos+1] << 8); } static u32 get_conf_long(struct device *d, unsigned int pos) { return d->config[pos] | (d->config[pos+1] << 8) | (d->config[pos+2] << 16) | (d->config[pos+3] << 24); } /* Sorting */ static int compare_them(const void *A, const void *B) { const struct pci_dev *a = (*(const struct device **)A)->dev; const struct pci_dev *b = (*(const struct device **)B)->dev; if (a->bus < b->bus) return -1; if (a->bus > b->bus) return 1; if (a->dev < b->dev) return -1; if (a->dev > b->dev) return 1; if (a->func < b->func) return -1; if (a->func > b->func) return 1; return 0; } static void sort_them(void) { struct device **index, **h, **last_dev; int cnt; struct device *d; cnt = 0; for(d=first_dev; d; d=d->next) cnt++; h = index = alloca(sizeof(struct device *) * cnt); for(d=first_dev; d; d=d->next) *h++ = d; qsort(index, cnt, sizeof(struct device *), compare_them); last_dev = &first_dev; h = index; while (cnt--) { *last_dev = *h; last_dev = &(*h)->next; h++; } *last_dev = NULL; } /* Normal output */ static void show_bases(struct device *d, int cnt) { struct pci_dev *p = d->dev; word cmd = get_conf_word(d, PCI_COMMAND); int i; for(i=0; ibase_addr[i]; u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (flg == 0xffffffff) flg = 0; if (!pos && !flg) continue; printf("\tRegion %d: ", i); if (pos && !flg) /* Reported by the OS, but not by the device */ { printf("[virtual] "); flg = pos; } if (flg & PCI_BASE_ADDRESS_SPACE_IO) { pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK; printf("I/O ports at "); if (a) { portbase = (unsigned int) a; printf(IO_FORMAT, a); } else if (flg & PCI_BASE_ADDRESS_IO_MASK) printf(""); else printf(""); if (!(cmd & PCI_COMMAND_IO)) printf(" [disabled]"); } else { int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK; pciaddr_t a = pos & PCI_ADDR_MEM_MASK; int done = 0; u32 z = 0; printf("Memory at "); if (t == PCI_BASE_ADDRESS_MEM_TYPE_64) { if (i >= cnt - 1) { printf("\n"); done = 1; } else { i++; z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i); if (buscentric_view) { if (a || z) printf("%08x" ADDR_FORMAT, z, a); else printf(""); done = 1; } } } if (!done) { if (a) printf(ADDR_FORMAT, a); else printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "" : ""); } printf(" (%s, %sprefetchable)", (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" : (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" : (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3", (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); if (!(cmd & PCI_COMMAND_MEMORY)) printf(" [disabled]"); } putchar('\n'); } } static void show_htype0(struct device *d) { unsigned long rom = d->dev->rom_base_addr; show_bases(d, htype0_cnt); if (rom & 1) printf("\tExpansion ROM at %08lx%s\n", rom & PCI_ROM_ADDRESS_MASK, (rom & PCI_ROM_ADDRESS_ENABLE) ? "" : " [disabled]"); if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) { int where = get_conf_byte(d, PCI_CAPABILITY_LIST); while (where) { int id, next, cap; printf("\tCapabilities: "); if (!config_fetch(d, where, 4)) { puts(""); break; } id = get_conf_byte(d, where + PCI_CAP_LIST_ID); next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT); cap = get_conf_word(d, where + PCI_CAP_FLAGS); printf("[%02x] ", where); if (id == 0xff) { printf("\n"); break; } switch (id) { case PCI_CAP_ID_PM: printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); break; case PCI_CAP_ID_AGP: break; default: printf("#%02x [%04x]", id, cap); } where = next; } } } static struct bus * find_bus(struct bridge *b, unsigned int n) { struct bus *bus; for(bus=b->first_bus; bus; bus=bus->sibling) if (bus->number == n) break; return bus; } static struct bus * new_bus(struct bridge *b, unsigned int n) { struct bus *bus = xmalloc(sizeof(struct bus)); bus = xmalloc(sizeof(struct bus)); bus->number = n; bus->sibling = b->first_bus; bus->first_dev = NULL; bus->last_dev = &bus->first_dev; b->first_bus = bus; return bus; } static void insert_dev(struct device *d, struct bridge *b) { struct pci_dev *p = d->dev; struct bus *bus; if (! (bus = find_bus(b, p->bus))) { struct bridge *c; for(c=b->child; c; c=c->next) if (c->secondary <= p->bus && p->bus <= c->subordinate) return insert_dev(d, c); bus = new_bus(b, p->bus); } /* Simple insertion at the end _does_ guarantee the correct order as the * original device list was sorted by (bus, devfn) lexicographically * and all devices on the new list have the same bus number. */ *bus->last_dev = d; bus->last_dev = &d->next; d->next = NULL; } /* Bus mapping mode */ static void do_map_bridges(int bus, int min, int max) { struct bus_info *bi = bus_info + bus; struct bus_bridge *b; bi->guestbook = 1; for(b=bi->bridges; b; b=b->next) { if (bus_info[b->first].guestbook) b->bug = 1; else if (b->first < min || b->last > max) b->bug = 2; else { bus_info[b->first].via = b; do_map_bridges(b->first, b->first, b->last); } } } /* Show hexadecimal dump of first 64 bytes of the PCI configuration space (the standard header). Useful for debugging of drivers and lspci itself. */ static void show_hex_dump(struct device *d) { unsigned int i; printf("Command reg: "); printf(" %02x", get_conf_byte(d, 5)); printf(" %02x", get_conf_byte(d, 4)); putchar('\t'); printf("Status reg: "); printf(" %02x", get_conf_byte(d, 7)); printf(" %02x", get_conf_byte(d, 6)); putchar('\n'); /* Note! the byte order is lsb msb */ printf("Base address regs: "); for(i=0x10; i<0x24; i++){ printf(" %02x", get_conf_byte(d, i)); } putchar('\n'); } // Lucent modem specific stuff. void dp_onhook_cmd(void) { #if 0 printf( "Should call cell_onhook()\n" ); dp_modem_command(0x13, 0, 0); x_output( 7); x_output(0x0e); x_output(0x14); x_output(0x10); if (byte_59ED2 == 0) { x_output(0x19); x_output( 3); x_output(0x12); } else byte_59ED2 = 0x0a; dp_write_dsp_ram(0xf20, 0x42f8); dp_regwrite(0xd8, 0xff); dp_regwrite(0xb7, 0xff); /* dp_tad_downloaded = dp_fax_downloaded = 0; */ if (byte_59ED4 == 1) { byte_59ED4 = 0; byte_59EB2 = 0; } v8bis_app_reset(); dp_init_local_phone_state(); V34Mode = 0; dp_update_diagnostics(); if (x_status != 0) goto l2D1; x_status = 1; ll_save_diagnostics(); l2D1: if (byte_59ED2 != 0) goto l2E7; if (x_modem_mode == 3) goto l2E7; dp_run_rom(); l2E7: dp_first_call = 0; #endif } void go_onhook(void) { dp_onhook_cmd(); } void io_init(void) { struct pci_dev *p = modem_dev->dev; bool bMarsChipset; /* Only cards with device ID 044? are mars chipset based. */ bMarsChipset = ((p->device_id & 0xfff0) == 0x0440); // Set up the port IO. port_io_init(io_address[1], io_address[2], bMarsChipset); } @ 1.3 log @Added some changes from Pavel Machek . Added support for port offset. @ text @d2 1 a2 1 * $Id: ltmodem.c,v 1.2 1999/07/05 04:04:46 root Exp root $ d13 6 a18 1 #include "portIO.h" d22 1 a22 2 int main(int argc, char **argv) d26 3 d53 1 a53 1 while ((c = getopt(argc, argv, "im" )) != -1) { d59 27 d89 4 d94 4 a97 1 printf( "Usage: ltmodem [-i]\n" ); d101 1 a101 1 exit: d107 18 d162 2 a163 4 /* Show any found modem. */ static void show_modem(void) d334 2 a335 1 for (j=0; j #include #include #include #include #include #include "portIO.h" #include "irq.h" /* Format strings used for IRQ numbers and memory addresses */ #ifdef ARCH_SPARC64 #define IRQ_FORMAT "%08x" #else #define IRQ_FORMAT "%d" #endif #ifdef HAVE_64BIT_ADDRESS #define ADDR_FORMAT "%016Lx" #else #define ADDR_FORMAT "%08lx" #endif #ifdef ARCH_SPARC64 #define IO_FORMAT "%016Lx" #elif defined(HAVE_64BIT_ADDRESS) #define IO_FORMAT "%04Lx" #else #define IO_FORMAT "%04lx" #endif #define LTMODEM_VERSION "0.0.5" struct device { struct device *next; struct pci_dev *dev; unsigned int config_cnt; byte config[256]; }; /* Communication with libpci */ static struct pci_access *pacc; /* Our view of the PCI bus */ static struct device *first_dev; static struct device *modem_dev; /* Tree output */ struct bridge { struct bridge *chain; /* Single-linked list of bridges */ struct bridge *next, *child; /* Tree of bridges */ struct bus *first_bus; /* List of busses connected to this bridge */ unsigned int primary, secondary, subordinate; /* Bus numbers */ struct device *br_dev; }; struct bus { unsigned int number; struct bus *sibling; struct device *first_dev, **last_dev; }; /* Options */ static int modem; /* Boolean: modem has been found = 1 */ /*static int verbose; Show detailed information */ static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */ static struct pci_filter filter; /* Device filter */ /* general scanning stuff. */ static struct device * scan_device(struct pci_dev *p); static void scan_devices(void); static int check_root(void); static int config_fetch(struct device *d, unsigned int pos, unsigned int len); /* Config space accesses */ static inline byte get_conf_byte(struct device *d, unsigned int pos); static word get_conf_word(struct device *d, unsigned int pos); static u32 get_conf_long(struct device *d, unsigned int pos); /* Count used to access bases of htype0 devices. */ static int htype0_cnt = 6; /* Array to hold IO addresses and their width (in bytes). */ unsigned int io_address[6]; unsigned int io_length[6]; /* The number of I/O ports found, = length of io_address. */ static unsigned int io_cnt; /* Sorting */ static int compare_them(const void *A, const void *B); static void sort_them(void); /* Normal output */ #define FLAG(x,y) ((x & y) ? '+' : '-') static void show_bases(struct device *d, int cnt); static void show_htype0(struct device *d); static struct bus * find_bus(struct bridge *b, unsigned int n); static struct bus * new_bus(struct bridge *b, unsigned int n); static void insert_dev(struct device *d, struct bridge *b); /* Bus mapping mode */ struct bus_bridge { struct bus_bridge *next; byte this, dev, func, first, last, bug; }; struct bus_info { byte exists; byte guestbook; struct bus_bridge *bridges, *via; }; static struct bus_info *bus_info; static void do_map_bridges(int bus, int min, int max); /* Show hexadecimal dump of first 64 bytes of the PCI configuration space (the standard header). */ static void show_hex_dump(struct device *d); /* Lucent modem specific stuff. */ static int find_modem(void); static void show_modem(void); /* Modem monitoring functions. */ static void monitor_modem(void); static int set_monitoring_interval(void); static void continous_monitoring(int monitor_type, int monitoring_interval); static void redisplay_modem_regs(void); /* Modem writing functions. */ static void set_modem(void); /* Interactively set the control register. */ static void set_modem_cont_reg(void); /* Interactively write to the IO ports. */ static void set_modem_io(void); /* Main command menu. */ void main_menu(void); void setup_irq(void); void io_init(void); @ 1.3 log @See changes to ltmodem.c @ text @d2 1 a2 1 * $Id: ltmodem.h,v 1.2 1999/07/05 03:59:31 root Exp root $ a15 1 #include d18 2 a19 1 #include "pciutils.h" d43 1 a43 1 #define LTMODEM_VERSION "0.0.4" d193 1 a193 2 void main_menu(void); d195 1 a195 3 /* Write functions prototypes from pciutils lib, for reference. int pci_write_byte(struct pci_dev *d, int pos, byte data); d197 1 a197 10 int pci_write_word(struct pci_dev *d, int pos, word data); int pci_write_long(struct pci_dev *d, int pos, u32 data); int pci_write_block(struct pci_dev *d, int pos, byte *buf, int len); */ @ 1.2 log @Added prototypes for new monitoring functions. @ text @d2 1 a2 1 * $Id: ltmodem.h,v 0.3 1999/07/05 03:51:27 root Exp root $ d43 1 a43 1 #define LTMODEM_VERSION "0.0.3" d108 3 a110 2 /* Array to hold IO addresses. */ int io_address[6]; d112 1 a112 1 static int io_cnt; a171 2 static int set_monitoring_type(void); @ 1.1 log @Initial revision @ text @d2 1 a2 1 * $Id: ltmodem.h,v 0.0.3 1999/07/04 22:45:57 rjmc Exp $ d169 1 a169 1 void d171 1 a171 1 int d174 1 a174 1 int d177 1 a177 1 void d180 1 a180 1 void d184 1 a184 1 void d187 1 a187 1 void d190 1 a190 1 void @ ltmodem-0.0.5/stdbool.h100644 0 0 766 6755203122 13046 0ustar rootroot/* stdbool.h for GNU. */ #ifndef __STDBOOL_H__ #define __STDBOOL_H__ 1 /* The type `bool' must promote to `int' or `unsigned int'. The constants `true' and `false' must have the value 0 and 1 respectively. */ typedef enum { false = 0, true = 1 } bool; /* The names `true' and `false' must also be made available as macros. */ #define false false #define true true /* Signal that all the definitions are present. */ #define __bool_true_false_are_defined 1 #endif /* stdbool.h */ ltmodem-0.0.5/HAL.c100444 0 0 5142 6755710513 12015 0ustar rootroot/* * $Id: HAL.c,v 1.3 1999/08/16 04:19:23 root Exp $ * * HAL interface for Lucent PCI modem software. * * Copyright (c) 1999 Richard J.M. Close * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "HAL.h" // This is my Linux implemetation of the NT HAL library routines used by the // driver. The implementation in this file is not a copy of the real code but // has the same interface and is designed to be used by user space processes. // A version for a device driver will be implemented at a later date, this // will be much simpler as more system resources are available to drivers running // at the kernel level. // IO routines. // // Read a long word. unsigned int READ_PORT_ULONG (unsigned short Port) { unsigned int Value = 0; int i; // Read from the port. // Value = inl(Port); Doesn't work correctly! repeats first two bytes. for (i=0; i<4; i++) { // Not sure of the byte order! Value = Value * 256; Value = Value + inb(Port + i); } return Value; } // Write a long word. void WRITE_PORT_ULONG (unsigned short Port, unsigned int Value) { // Write to port. outl(Value, Port); } // Read a short word. unsigned short READ_PORT_USHORT (unsigned short Port) { // Read from the port. return inw(Port); } // Write a byte. void WRITE_PORT_USHORT (unsigned short Port, unsigned short Value) { // Write to port. outw(Value, Port); } // Read a byte. unsigned char READ_PORT_UCHAR (unsigned short Port) { // Read from the port. return inb(Port); } // Write a short word. void WRITE_PORT_UCHAR (unsigned short Port, unsigned char Value) { // Write to port. outb(Value, Port); } // Timer related stuff. void KeQueryTickCount(unsigned long* TickCount) { // KeQueryTickCount maintains a count of the interval timer interrupts // that have occurred since the system was booted. // Parameters // TickCount // Points to the tick count value on return from KeQueryTickCount. //Comments // The TickCount value increases by one at each interval timer interrupt // while the system is running. // The preferred method of determining elapsed time is by using TickCount // for relative timing and time stamps. // To determine the absolute elapsed time multiply the returned TickCount // by the KeQueryTimeIncrement return value using compiler support for 64-bit // integer operations. *TickCount = 0; } /* ULONG     KeQueryTimeIncrement(         ); KeQueryTimeIncrement returns the number of 100-nanosecond units that are added to the system time each time the interval clock interrupts. */ ltmodem-0.0.5/HAL.h100444 0 0 2402 6746737161 12026 0ustar rootroot/* * $Id: HAL.h,v 1.1 1999/07/26 01:48:33 root Exp $ * * HAL interface for Lucent PCI modem software. * * Copyright (c) 1999 Richard J.M. Close * * Can be freely distributed and used under the terms of the GNU GPL. */ #ifndef HAL_H #define HAL_H #include #include // This is my Linux implemetation of the NT HAL library routines used by the // driver. The implementation in this file is not a copy of the real code but // has the same interface and is currently designed to be used by user space // processes. // A version for a device driver will be implemented at a later date, this // will be much simpler as more system resources are available to drivers running // at the kernel level. // IO routines. // Read a long word. unsigned int READ_PORT_ULONG (unsigned short Port); // Write a long word. void WRITE_PORT_ULONG (unsigned short Port, unsigned int Value); // Read a short word (2 bytes). unsigned short READ_PORT_USHORT (unsigned short Port); // Write a long word (2 bytes). void WRITE_PORT_USHORT (unsigned short Port, unsigned short Value); // Read a byte. unsigned char READ_PORT_UCHAR (unsigned short Port); // Write a byte. void WRITE_PORT_UCHAR (unsigned short Port, unsigned char Value); #endif /* HAL_H */ ltmodem-0.0.5/HAL.h,v100444 0 0 2667 6746737161 12305 0ustar rootroothead 1.1; access; symbols; locks; strict; comment @ * @; 1.1 date 99.07.26.01.48.33; author root; state Exp; branches; next ; desc @@ 1.1 log @Initial revision @ text @/* * $Id: HAL.h,v 1.0 1999/07/21 03:30:34 root Exp root $ * * HAL interface for Lucent PCI modem software. * * Copyright (c) 1999 Richard J.M. Close * * Can be freely distributed and used under the terms of the GNU GPL. */ #ifndef HAL_H #define HAL_H #include #include // This is my Linux implemetation of the NT HAL library routines used by the // driver. The implementation in this file is not a copy of the real code but // has the same interface and is currently designed to be used by user space // processes. // A version for a device driver will be implemented at a later date, this // will be much simpler as more system resources are available to drivers running // at the kernel level. // IO routines. // Read a long word. unsigned int READ_PORT_ULONG (unsigned short Port); // Write a long word. void WRITE_PORT_ULONG (unsigned short Port, unsigned int Value); // Read a short word (2 bytes). unsigned short READ_PORT_USHORT (unsigned short Port); // Write a long word (2 bytes). void WRITE_PORT_USHORT (unsigned short Port, unsigned short Value); // Read a byte. unsigned char READ_PORT_UCHAR (unsigned short Port); // Write a byte. void WRITE_PORT_UCHAR (unsigned short Port, unsigned char Value); #endif /* HAL_H */ @ ltmodem-0.0.5/HAL.c,v100444 0 0 16033 6755710513 12300 0ustar rootroothead 1.3; access; symbols; locks; strict; comment @ * @; 1.3 date 99.08.16.04.19.23; author root; state Exp; branches; next 1.2; 1.2 date 99.07.26.02.35.25; author root; state Exp; branches; next 1.1; 1.1 date 99.07.26.01.48.59; author root; state Exp; branches; next ; desc @@ 1.3 log @Tidy to make it compatible with Pavel's latest changes. @ text @/* * $Id: HAL.c,v 1.2 1999/07/26 02:35:25 root Exp root $ * * HAL interface for Lucent PCI modem software. * * Copyright (c) 1999 Richard J.M. Close * * Can be freely distributed and used under the terms of the GNU GPL. */ #include "HAL.h" // This is my Linux implemetation of the NT HAL library routines used by the // driver. The implementation in this file is not a copy of the real code but // has the same interface and is designed to be used by user space processes. // A version for a device driver will be implemented at a later date, this // will be much simpler as more system resources are available to drivers running // at the kernel level. // IO routines. // // Read a long word. unsigned int READ_PORT_ULONG (unsigned short Port) { unsigned int Value = 0; int i; // Read from the port. // Value = inl(Port); Doesn't work correctly! repeats first two bytes. for (i=0; i<4; i++) { // Not sure of the byte order! Value = Value * 256; Value = Value + inb(Port + i); } return Value; } // Write a long word. void WRITE_PORT_ULONG (unsigned short Port, unsigned int Value) { // Write to port. outl(Value, Port); } // Read a short word. unsigned short READ_PORT_USHORT (unsigned short Port) { // Read from the port. return inw(Port); } // Write a byte. void WRITE_PORT_USHORT (unsigned short Port, unsigned short Value) { // Write to port. outw(Value, Port); } // Read a byte. unsigned char READ_PORT_UCHAR (unsigned short Port) { // Read from the port. return inb(Port); } // Write a short word. void WRITE_PORT_UCHAR (unsigned short Port, unsigned char Value) { // Write to port. outb(Value, Port); } // Timer related stuff. void KeQueryTickCount(unsigned long* TickCount) { // KeQueryTickCount maintains a count of the interval timer interrupts // that have occurred since the system was booted. // Parameters // TickCount // Points to the tick count value on return from KeQueryTickCount. //Comments // The TickCount value increases by one at each interval timer interrupt // while the system is running. // The preferred method of determining elapsed time is by using TickCount // for relative timing and time stamps. // To determine the absolute elapsed time multiply the returned TickCount // by the KeQueryTimeIncrement return value using compiler support for 64-bit // integer operations. *TickCount = 0; } /* ULONG     KeQueryTimeIncrement(         ); KeQueryTimeIncrement returns the number of 100-nanosecond units that are added to the system time each time the interval clock interrupts. */ @ 1.2 log @Added code so IO permission level is only changed if port address is greater than 0x3ff, as this is not needed for ports up to 0x3ff. @ text @d2 1 a2 1 * $Id: HAL.c,v 1.1 1999/07/26 01:48:59 root Exp root $ d29 10 a38 23 unsigned int Value = 0; unsigned char i; // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: READ_PORT_ULONG()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Read from the port. // Value = inl(Port); Doesn't work correctly! repeats first two bytes. Value = 0; for (i=0; i<4; i++) { // Not sure of the byte order! Value = Value * 256; Value = Value + inb(Port + i); } // Free the ports. if (Port > 0x3ff) iopl(0); } return Value; d45 2 a46 13 // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: WRITE_PORT_ULONG()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Write to port. outl(Value, Port); // Free the ports. if (Port > 0x3ff) iopl(0); } d52 2 a53 17 unsigned short Value = 0; // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: READ_PORT_USHORT()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Read from the port. Value = inw(Port); // Free the ports. if (Port > 0x3ff) iopl(0); } return Value; d59 2 a60 13 // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: WRITE_PORT_USHORT()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Write to port. outw(Value, Port); // Free the ports. if (Port > 0x3ff) iopl(0); } d66 3 a68 14 unsigned char Value = 0; // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: READ_PORT_UCHAR()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Read from the port. Value = inb(Port); // Free the ports. if (Port > 0x3ff) iopl(0); } d70 2 a71 1 return Value; d73 2 a76 2 // Write a short word. void WRITE_PORT_UCHAR (unsigned short Port, unsigned char Value) { d78 1 a78 12 // Get access to all of I/O space if needed. if (Port > 0x3ff) if (iopl(3) < 0) { perror("portIO: WRITE_PORT_UCHAR()"); fprintf(stderr, "This program must be run as root.\n"); } else { // Write to port. outb(Value, Port); // Free the ports. if (Port > 0x3ff) iopl(0); } a79 1 } d81 1 d83 2 d86 3 d90 1 d92 2 d95 2 d98 3 d102 1 d104 1 d106 4 d111 2 d114 1 @ 1.1 log @Initial revision @ text @d2 1 a2 1 * $Id: HAL.h,v 1.0 1999/07/21 03:30:34 root Exp root $ d32 6 a37 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: READ_PORT_ULONG()"); fprintf(stderr, "This program must be run as root.\n"); } d48 1 a48 1 iopl(0); d58 6 a63 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: WRITE_PORT_ULONG()"); fprintf(stderr, "This program must be run as root.\n"); } d68 1 a68 1 iopl(0); d78 6 a83 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: READ_PORT_USHORT()"); fprintf(stderr, "This program must be run as root.\n"); } d88 1 a88 1 iopl(0); d98 6 a103 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: WRITE_PORT_USHORT()"); fprintf(stderr, "This program must be run as root.\n"); } d108 1 a108 1 iopl(0); d118 6 a123 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: READ_PORT_UCHAR()"); fprintf(stderr, "This program must be run as root.\n"); } d128 1 a128 1 iopl(0); d138 6 a143 5 // Get access to all of I/O space. if (iopl(3) < 0) { perror("portIO: WRITE_PORT_UCHAR()"); fprintf(stderr, "This program must be run as root.\n"); } d148 1 a148 1 iopl(0); @ ltmodem-0.0.5/make_i2sig100755 0 0 252 6753710621 13162 0ustar rootrootgcc -D__KERNEL__ -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -m386 -DCPU=386 -DMODULE -c -o i2sig.o i2sig.c ltmodem-0.0.5/irq.h100644 0 0 255 6755152312 12170 0ustar rootroot#ifndef LT_IRQ_H #define LT_IRQ_H #include #include #include "portIO.h" void signal_handler(int i); void signal_init(void); #endif /* LT_IRQ_H */